On a big-little system, PMUs can be wired to CPUs using per CPU
interrups (PPI). In this case, it is important to make sure that
the enable/disable do happen on the right set of CPUs.

So instead of relying on the interrupt-affinity property, we can
use the actual percpu affinity that DT exposes as part of the
interrupt specifier. The DT binding is also updated to reflect
the fact that the interrupt-affinity property shouldn't be used
in that case.
Acked-by: NRob Herring <robh@kernel.org>
Tested-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>

Add a "uefi" node under /hypervisor node in FDT, then Linux kernel could
scan this to get the UEFI information.

CC: Rob Herring <robh@kernel.org>
Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
Tested-by: NJulien Grall <julien.grall@arm.com>

This commit adds the DT binding documentation for the Marvell CP110
system controller, which is part of the CP110 HW block, itself used in
the Marvell Armada 7K and 8K SoCs.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NRob Herring <rob@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Document the DT bindings for controlling ARM PL310 Power Control
settings.

Discussion on the binding wording:
http://archive.arm.linux.org.uk/lurker/message/20160427.143444.5141d302.en.htmlSigned-off-by: NBrad Mouring <brad.mouring@ni.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The System Trace Macrocell (STM) is an IP block falling under the
CoreSight umbrella.  It's main purpose it so expose stimulus channels
to any system component for the purpose of information logging.

Bindings for this IP block adds a couple of items to the current
mandatory definition for CoreSight components.
Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Use "rockchip,rk3399-evb" compatible string for Rockchip RK3399
evaluation board.
Signed-off-by: NJianqun Xu <jay.xu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch adds documentation for the devicetree bindings used by
the DT files of Hisilicon Hip06 D03 board.

Meanwhile, reorder the soc/board name alphabetically.
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

Currently ARM CPUs DT bindings allows different enable-method value for
PSCI based systems. On ARM 64-bit this property is required and must be
"psci" while on ARM 32-bit systems this property is optional and must
be "arm,psci" if present.

However, "arm,psci" has always been the compatible string for the PSCI
node, and was never intended to be the enable-method. So this is a bug
in the binding and not a deliberate attempt at specifying 32-bit
differently.

This is problematic if 32-bit OS is run on 64-bit system which has
"psci" as enable-method rather than the expected "arm,psci".

So let's unify the value into "psci" and remove support for "arm,psci"
before it finds any users.
Reported-by: NSoby Mathew <Soby.Mathew@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Signed-off-by: NEric Engestrom <eric@engestrom.ch>
Signed-off-by: NRob Herring <robh@kernel.org>

Document the compatible string for Broadcom Vulcan PMU.
Also arranged the list in alphabetical order.
Signed-off-by: NAshok Kumar <ashoks@broadcom.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

The MiQi is a rk3288-based devboard from Shenzen based mqmaker, with a
footprint the size of a credit card.

Main available outside connections are 4 usb ports, hdmi, gigabit
ethernet and two expansion headers.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Commit eb3fcf00 ("dt-bindings: consolidate interrupt controller
bindings") moved the binding documentation for the ARM GIC from
arm/gic.txt to interrupt-controller/arm,gic.txt. However, there are
still some binding documents referring to the old path. Update these
binding documents to use the correct location.

Fixes: eb3fcf00 ("dt-bindings: consolidate interrupt controller bindings")
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NRob Herring <robh@kernel.org>

Add power-domain binding documentation for the NVIDIA PMC driver in
order to support generic power-domains.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The AM572x-IDK board is a board based on TI's AM5728 SOC
which has a dual core 1.5GHz A15 processor. This board is a
development platform for the Industrial market with:
- 2GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector

The link to the data sheet and TRM can be found here:

http://www.ti.com/product/AM5728

This patch creates a common dtsi file that will provide a common board
dtsi file to define the nodes that are common to AM57xx (including the
upcoming AM5718) IDK boards.

Initial support is only for basic peripherals
Signed-off-by: NSchuyler Patton <spatton@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

TI's Industrial Communication Engine EVM is a low cost hardware mainly
developed for industrial communication type applications using serial
or Ethernet based interfaces. This platform features TI's AM3359 with
800MHz single core Cortex-A8 processor, 256MB DDR3, 64MB SPI flash,
8MB NOR Flash, mmc, usb, can, dual Ethernet ports.

For more information, look at HW user guide[1], Data manual[2].

Just add basic support for the moment.

[1] http://processors.wiki.ti.com/index.php/AM335x_Industrial_Communication_Engine_EVM_Rev2_1_HW_User_Guide
[2] http://www.ti.com/lit/ds/symlink/am3359.pdfSigned-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The new shutdown controller compatible with sama5d2 has a new binding
documentation and properties.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NSebastian Reichel <sre@kernel.org>

Add the PMC driver compatible strings for Tegra132 and Tegra210.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The ARM Versatile has an optional daughterboard, if this is
mounted, we need to be able to access its system controller.
Put in a documentation blurb for this.

Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the device tree bindings needed to support the Altera On-Chip
RAM ECC on the Arria10 chip.
Signed-off-by: NThor Thayer <tthayer@opensource.altera.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1459450087-24792-5-git-send-email-tthayer@opensource.altera.comSigned-off-by: NBorislav Petkov <bp@suse.de>

This commit adds the Device Tree binding documentation for the system
controller found in Marvell AP806 HW block, which is one of the core
HW blocks of the 64-bits Marvell Armada 7K/8K family.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds the Device Tree source for Samsung ARTIK5 module[1]
based on Exynos3250 SoC. The ARTIK5 module includes the following
devices:
 - Application Processor (Samsung Exynos3250)
 - WiFi/BT Combo chip (Broadcom4354)
 - PMIC (Samsung S2MPS14)
 - eMMC (4GB)
 - DRAM LPDDR3 (512MB)
 - Connectors pin (60 Pins x 3 set)

Also, this patch adds the ARTIK5 evaluation board[2] dts file which includes
the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
ethernet port, uart port and so on.

[1] https://www.artik.io/hardware/artik-5
[2] http://www.digikey.com/product-search/en?FV=ffecca14Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NAndi Shyti <andi.shyti@samsung.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>

Use "geekbuying,geekbox" compatible string.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add compatible strings for Amlogic S905/GXBB based boards: Hardkernel
ODROID-C2, Amlogic P200 and Amlogic P201.

Cc: devicetree@vger.kernel.org
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

So far, the CIDR and EXID registers were in the DBGU interface. This device
has disappeared with the SAMA5D2 family. These registers are exposed
through a new device called chipid.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
[nicolas.ferre@atmel.com: remove useless warnings]
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
[arnd@arndb.de: suggest to use static functions to reduce scope]
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This SFR node is looked up by the I2S controller driver to tune the
SFR_I2SCLKSEL register.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add the device tree bindings needed to support the Altera L2 cache on
the Arria10 chip. Since all the peripherals share IRQs, the IRQ fields
are now in the ecc_manager.
Signed-off-by: NThor Thayer <tthayer@opensource.altera.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1458576106-24505-7-git-send-email-tthayer@opensource.altera.comSigned-off-by: NBorislav Petkov <bp@suse.de>

Use "tronsmart,vega-s95" as well as
    "tronsmart,vega-s95-pro",
    "tronsmart,vega-s95-meta" and
    "tronsmart,vega-s95-telos" compatible strings.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

Use "amlogic,meson-gxbb" compatible string.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NCarlo Caione <carlo@endlessm.com>

Introduce a dt property, ti,no-idle, that prevents an IP to idle at any
point. This is to handle Errata i877, which tells that GMAC clocks
cannot be disabled.
Acked-by: NRoger Quadros <rogerq@ti.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

There are two distinct RealView EB system controller that we need
to detect and handle because their register layout differ
slightly.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NRob Herring <robh@kernel.org>

The binding documentation uses both "uVolt" and "uV" for micro-volt.
Improve consistency by settling on "uV".
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NRob Herring <robh@kernel.org>

Add ARM CoreLink CCI-550  cache coherent interconnect PMU
driver support. The CCI-550 PMU shares all the attributes of CCI-500
PMU, except for an additional master interface (MI-6 - 0xe).
CCI-550 requires the same work around as for CCI-500 to
write to the PMU counter.
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NPunit Agrawal <punit.agrawal@arm.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

This commit adds the base Device Tree files for the Armada 7K and 8K
SoCs, as well as the Armada 8040 DB board.

The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are
composed of:

 - An AP806 block that contains the CPU core and a few basic
   peripherals. The AP806 is available in dual core configurations
   (used in 7020 and 8020) and quad core configurations (used in 8020
   and 8040).

 - One or two CP110 blocks that contain all the high-speed interfaces
   (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110,
   and the 8K family chips have two CP110, giving them twice the
   number of HW interfaces.

In order to represent this from a Device Tree point of view, this
commit creates the following hierarchy:

 * armada-ap806.dtsi - definitions common to dual/quad ap806
   * armada-ap806-dual.dtsi - description of the two CPUs
     * armada-7020.dtsi - description of the 7020 SoC
     * armada-8020.dtsi - description of the 8020 SoC
   * armada-ap806-quad.dtsi - description of the four CPUs
     * armada-7040.dtsi - description of the 7040 SoC
       * armada-7040-db.dts - description of the 7040 board
     * armada-8040.dtsi - description of the 8040 SoC

The CP110 blocks are not described yet, and will be part of future
patch series.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

K2G SoC family is the newest version of the Keystone family of processors.

The technical reference manual for K2G can be found here:
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf

Add new bindings for K2G and the K2G evm. Also document these new bindings.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

This adds device tree bindings for the Artpec-6 SoC.
Signed-off-by: NLars Persson <larper@axis.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Some qcom based bootloaders identify the dtb blob based on a set
of device properties like SoC, platform, PMIC, and revisions of
those components. In downstream kernels, these values are added
to the different component dtsi files (i.e. pmic dtsi file, SoC
dtsi file, board dtsi file, etc.) via qcom specific DT
properties. The dtb files are parsed by a program called dtbTool
that picks out these properties and creates a table of contents
binary blob with the property information and some offsets into
the concatenation of all the dtbs (termed a QCDT image).

The suggestion is to do this via the board compatible string
instead, because these qcom specific properties are never used by
the kernel. Add a document describing the format of the
compatible string that encodes all this information that's
currently encoded in the qcom,{msm-id,board-id,pmic-id}
properties in downstream devicetrees. Future bootloaders may be
updated to look at the compatible field instead of looking for
the table of contents image. For non-updateable bootloaders, a
new dtbTool program will parse the compatible string and generate
a QCDT image from it.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Document the compatible string for the Kryo family of qcom cpus.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Update arm/cpus.txt to add "brcm,vulcan" CPU. Add documentation
for Broadcom Vulcan boards in arm/bcm/brcm,vulcan-soc.txt
Signed-off-by: NJayachandran C <jchandra@broadcom.com>