Implement clock and power gating support for tonga.  On Tonga
this is handles by the SMU rather than direct register settings
in the driver.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Add callbacks interface for clock and powergating.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Interface for clock and power gating handling.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Implement displaygap programming for tonga.  This is
required for properly mclk switching.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Add support for display configuration changes to the event manager.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This allows the eventmgr to properly update the displaygap on
certain power events.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Displaygap support is required for proper mclk switching.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Switch over to handling in the powerplay module.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NEric Huang <JinHuiEric.Huang@amd.com>

This option can be used to enable the new powerplay implementation,
and it is disabled by default.
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This enabled DPM support for Fiji.  DPM is dynamic
clock and voltage scaling.

v2: rename fiji_hwmgr_early_init to fiji_hwmgr_init
v3: (agd) fold in endian fix, additional function addition
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NEric Huang <JinHuiEric.Huang@amd.com>

Add support for the SMU manager for Fiji. This handles the
firmware loading for other IP blocks (GFX, SDMA, etc.).
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NEric Huang <JinHuiEric.Huang@amd.com>

Add some new functions to support Fiji.  Split out
from the previous patch.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NEric Huang <JinHuiEric.Huang@amd.com>

New headers for Fiji.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NEric Huang <JinHuiEric.Huang@amd.com>

This implements DPM for tonga.  DPM handles dynamic
clock and voltage scaling.

v2: merge all the patches related with tonga dpm
v3: merge dpm force level fix, cgs display fix, spelling fix
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Nyanyang1 <young.yang@amd.com>
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NEric Huang <JinHuiEric.Huang@amd.com>

The SMU manager handles firmware loading for other IP
blocks (GFX, SDMA, etc.).  This implements it for Tonga.

v3: delete peci sub-module
v2: use cgs interface directly
Signed-off-by: NYoung Yang <Young.Yang@amd.com>
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

These headers provide the SMU interface used by the driver.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: Nyanyang1 <young.yang@amd.com>

Move smu7.h, smu7_discrete.h and smu7_fusion.h from amdgpu to powerplay.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: Nyanyang1 <young.yang@amd.com>

Add ixSWRST_COMMAND_1 in bif_5_0_d.h.  Required by
new powerplay code for tonga and fiji.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: Nyanyang1 <young.yang@amd.com>

This is the common interface for interacting with the powerplay
module.

v2: squash in fixes
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Acked-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

The event manager handles power related driver events.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This adds clock and powergating support for CZ.

v2: squash in fixes
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This patch enables basic DPM support for Carrizo.
DPM handles dynamic clock and voltage scaling.

v3: delete peci sub-module
v2: use cgs interface directly
    correct define SMU_EnabledFeatureScoreboard_SclkDpmOn
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the SMU firmware manager interface for CZ.
Some header files are moved from amdgpu folder to powerplay as well.

v3: delete peci sub-module.
v2: use cgs interface directly
    add load_mec_firmware function
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

The hwmgr handles all hardware related calls, including clock/power
gating control, DPM, read and parse PPTable, etc.

v5: squash in fixes
v4: implement acpi's atcs function use cgs interface
v3: fix code style error and add big-endian mode support.
v2: use cgs interface directly in hwmgr sub-module
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

The SMUMGR is one sub-component of powerplay for SMU firmware support.
The SMU handles firmware loading for other IP blocks (GFX, SDMA, etc.)
on VI parts.  The adds the core powerplay infrastructure to handle that.

v3: direct use printk in powerplay module.
v2: direct use cgs_read/write_register functions in smu-modules
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Update amdgpu to deal with the new powerplay module properly.

v2: squash in fixes
v3: squash in Rex's power state reporting fix
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Acked-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Powerplay will use a different interface once it's integrated.  These
legacy pathes will be removed once powerplay is enabled by default.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

amdgpu_pp_ip_funcs is introduced to handle the two code paths,
the legacy one and the new powerplay implementation.

CONFIG_DRM_AMD_POWERPLAY kernel configuration option is
introduced for the powerplay component.

v4: squash in fixes
v3: register debugfs file when powerplay module enable
v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Add new CGS interfaces to query display info across modules.
This is nedded by the powerplay module for synchronizing with
the display module.

v2: (agd): fold in refresh rate fix, rebase
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Add a query to get the bus number and function of the
device.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>

Add a new driver internal interface for accessing ACPI
methods.  These will be used by various new components
including powerplay.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This will be shared with the new powerplay module.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

These will be shared with the new powerplay module.
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

rename amdgpu_pm_state_type to amd_pm_state_type
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Acked-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Combine the two quirks.

bug:
https://bugzilla.kernel.org/show_bug.cgi?id=109481Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

eaddr is sometimes treated as the last address inside the address
range, and sometimes as the first address outside the range. This
was resulting in errors when a test filled up the entire address
space. Make it consistent to always be the last address within the
range.
Signed-off-by: NFelix.Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org

eoffset is sometimes treated as the last address inside the address
range, and sometimes as the first address outside the range. This
was resulting in errors when a test filled up the entire address
space. Make it consistent to always be the last address within the
range. Also fixed related errors when checking the VA limit and in
radeon_vm_fence_pts.
Signed-off-by: NFelix.Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org

Need to properly handle the max link rate in the dpcd.
This prevents some cases where 5.4 Ghz is selected when
it shouldn't be.

v2: simplify logic, add array bounds check
Reviewed-by: NTom St Denis <tom.stdenis@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>