1. 29 4月, 2014 2 次提交
  2. 26 3月, 2014 2 次提交
  3. 18 3月, 2014 1 次提交
  4. 12 3月, 2014 2 次提交
  5. 07 3月, 2014 1 次提交
  6. 06 3月, 2014 1 次提交
  7. 05 3月, 2014 1 次提交
    • J
      gpio: add a driver for the Synopsys DesignWare APB GPIO block · 7779b345
      Jamie Iles 提交于
      The Synopsys DesignWare block is used in some ARM devices (picoxcell)
      and can be configured to provide multiple banks of GPIO pins.
      
      v12: - Add irq_startup/shutdown
           - do irq_create_mapping() in probe, irq_find_mapping() in to_irq()
           - Adjust mappings to show support for 1 gpio per port.
           - gpio-cells = <1>
      v11: - Use NULL when checking existence of 'interrupts' property
           - Bindings descriptions cleanup
      v10: - in documentation nr-gpio -> nr-gpios
      v9:  - cleanup in dt bindings doc
           - use of_get_child_count()
      v8:  - remove socfpga.dtsi changes
           - minor cleanup in devicetree documentation
      v7:  - use irq_generic_chip
           - support one irq per gpio line or one irq for many
           - s/bank/port/ and other cleanup
      v6:  - (atull) squash the set of patches
           - use linear irq domain
           - build fixes. Original driver was reviewed on v3.2.
           - Fix setting irq edge type for 'rising' and 'both'.
           - Support as a loadable module.
           - Use bgpio_chip's spinlock during register access.
           - Clean up register names to match spec
           - s/bank/port/ because register names use the word 'port'
           - s/nr-gpio/nr-gpios/
           - don't get/put the of_node
           - remove signoffs/acked-by's because of changes
           - other cleanup
      v5:  - handle sparse bank population correctly
      v3:  - depend on rather than select IRQ_DOMAIN
           - split IRQ support into a separate patch
      v2:  - use Rob Herring's irqdomain in generic irq chip patches
           - use reg property to indicate bank index
           - support irqs on both edges based on LinusW's u300 driver
      Signed-off-by: NJamie Iles <jamie@jamieiles.com>
      Signed-off-by: NAlan Tull <atull@altera.com>
      Reviewed-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      7779b345
  8. 27 2月, 2014 2 次提交
  9. 25 2月, 2014 1 次提交
  10. 13 2月, 2014 3 次提交
  11. 06 2月, 2014 1 次提交
  12. 05 2月, 2014 1 次提交
  13. 21 1月, 2014 1 次提交
    • M
      gpio: add LP3943 I2C GPIO expander driver · 0cc59b9d
      Milo Kim 提交于
      This is one of LP3943 MFD driver.
      LP3943 is configurable as a GPIO expander, up to 16 GPIOs.
      
      * Application note: how to configure LP3943 as a GPIO expander
        http://www.ti.com/lit/an/snva287a/snva287a.pdf
      
      * Supported GPIO controller operations
        request, free, direction_input, direction_output, get and set
      
      * GPIO direction register not supported
        LP3943 doesn't have the GPIO direction register. It only provides input and
        output status registers.
        So, private data for the direction should be handled manually.
        This variable is updated whenever the direction is changed and
        used in 'get' operation.
      
      * Pin assignment
        A driver data, 'pin_used' is checked when a GPIO is requested.
        If the GPIO is already assigned, then returns as failure.
        If the GPIO is available, 'pin_used' is set.
        When the GPIO is not used anymore, then it is cleared.
        It is defined as unsigned long type for atomic bit operation APIs,
        but only LSB 16bits are used because LP3943 has 16 outputs.
      Signed-off-by: NMilo Kim <milo.kim@ti.com>
      Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      0cc59b9d
  14. 20 1月, 2014 1 次提交
  15. 17 1月, 2014 1 次提交
    • L
      gpio: mcp23s08: Add irq functionality for i2c chips · 4e47f91b
      Lars Poeschel 提交于
      This adds interrupt functionality for i2c chips to the driver.
      They can act as a interrupt-controller and generate interrupts, if
      the inputs change.
      This is tested with a mcp23017 chip on an arm based platform.
      
      v3:
      - be a bit more clear that the irq functionality is also available
        on spi versions of the chips, but the linux driver does not support
        this yet
      
      v2:
      - some more word about irq-mirror property in binding doc
      - use of_read_bool instead of of_find_property for
        "interrupt-contrller" and "irq-mirror"
      - cache the "interrupt-controller" for remove function
      - do set the irq-mirror bit only if device is marked as
        interrupt-controller
      - do create the irq mapping and setup of irq_desc of all possible
        interrupts in probe path instead of in gpio_to_irq
      - mark gpios as in use as interrupts in irq in irq_startup and
        unlock it in irq_shutdown
      - rename virq to child_irq
      - remove dev argument from mcp23s08_irq_setup function
      - move gpiochip_add before mcp23s08_irq_setup in probe path
      Signed-off-by: NLars Poeschel <poeschel@lemonage.de>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      4e47f91b
  16. 08 1月, 2014 2 次提交
  17. 26 12月, 2013 1 次提交
  18. 20 12月, 2013 1 次提交
  19. 12 12月, 2013 2 次提交
    • B
      gpio: driver for Xtensa GPIO32 · 3b31d0ec
      Baruch Siach 提交于
      GPIO32 is a standard optional extension to the Xtensa architecture
      core that provides preconfigured output and input ports for intra
      SoC signaling. The GPIO32 option is implemented as 32bit Tensilica
      Instruction Extension (TIE) output state called EXPSTATE, and 32bit
      input wire called IMPWIRE. This driver treats input and output
      states as two distinct devices.
      
      v3:
      * Use BUG() in xtensa_impwire_set_value() to indicate that
        it should never be called (Linus Walleij)
      v2:
      * Address the comments of Linus Walleij:
        - Add a few comments
        - Expand commit log message
        - Use the BIT() macro for bit offsets
        - Rewrite CPENABLE handling as static inlines
        - Use device_initcall()
      * Depend on !SMP for reason explained in the comments (Marc Gauthier)
      * Use XCHAL_CP_ID_XTIOP to enable/disable GPIO32 only
      Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      3b31d0ec
    • A
      gpio: 74x164: Remove non-DT support · 61e73804
      Alexander Shiyan 提交于
      Commit 20bc4d5d
      (gpio: 74x164: Add support for the daisy-chaining) introduce check
      for DT for the driver, so driver cannot be used without DT.
      There are no in-tree users of this driver, so remove non-DT support
      completely.
      Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
      Acked-by: NMark Brown <broonie@linaro.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      61e73804
  20. 03 12月, 2013 2 次提交
  21. 06 11月, 2013 1 次提交
  22. 30 10月, 2013 1 次提交
  23. 26 10月, 2013 1 次提交
  24. 11 10月, 2013 1 次提交
  25. 21 9月, 2013 3 次提交
  26. 19 9月, 2013 1 次提交
  27. 13 9月, 2013 1 次提交
  28. 30 8月, 2013 1 次提交
    • S
      gpio: add GPIO support for F71882FG and F71889F · 6c17aa01
      Simon Guinot 提交于
      This patch adds support for the GPIOs found on the Fintek super-I/O
      chips F71882FG and F71889F.
      
      A super-I/O is a legacy I/O controller embedded on x86 motherboards. It
      is used to connect the low-bandwidth devices. Among others functions the
      F71882FG/F71889F provides: a parallel port, two serial ports, a keyboard
      controller, an hardware monitoring controller and some GPIO pins.
      
      Note that this super-I/Os are embedded on some Atom-based LaCie NASes.
      The GPIOs are used to control the LEDs and the hard drive power.
      
      Changes since v3:
      - Use request_muxed_region to protect the I/O ports against concurrent
        accesses.
      
      Changes since v2:
      - Remove useless NULL setters for driver data.
      
      Changes since v1:
      - Enhance the commit message by describing what is a Super-I/O.
      - Use self-explanatory names for the GPIO register macros.
      - Add a comment to explain the platform device and driver registration.
      - Fix gpio_get when GPIO is configured in input mode. I only had
        the hardware to check this mode recently...
      Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      6c17aa01
  29. 26 8月, 2013 1 次提交