- 29 4月, 2014 2 次提交
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由 Jean Delvare 提交于
GPIO_TIMBERDALE doesn't need an explicit dependency on HAS_IOMEM, because it depends on MFD_TIMBERDALE which itself depends on HAS_IOMEM already. Signed-off-by: NJean Delvare <jdelvare@suse.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
Now that the gpiolib irqchip helpers can support nested, threaded IRQ handlers, switch the TC3589x driver over to using this new infrastructure. Tested on the Ux500. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 26 3月, 2014 2 次提交
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由 Linus Walleij 提交于
This converts the PL061 driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This provides a function gpiochip_irqchip_add() to set up an irqchip for a GPIO controller, and a function gpiochip_set_chained_irqchip() to chain it to a parent irqchip. Most GPIOs are of the type where a number of lines form a cascaded interrupt controller chained onto the primary system interrupt controller (or further down the chain) so let's add this helper and factor the code to request the lines to be used as IRQs, the .to_irq() function and the irqdomain into the core as well. Acked-by: NThomas Gleixner <tglx@linutronix.de> Acked-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 18 3月, 2014 1 次提交
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由 Alexander Shiyan 提交于
SYSCON driver was designed for using memory areas (registers) that are used in several subsystems. There are systems (CPUs) which use bits in one register for various purposes and thus should be handled by various kernel subsystems. This driver allows you to use the individual SYSCON bits as GPIOs. ARM CLPS711X SYSFLG1 input lines has been added as first user of this driver. Signed-off-by: NAlexander Shiyan <shc_work@mail.ru> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 12 3月, 2014 2 次提交
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由 Geert Uytterhoeven 提交于
Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jean Delvare 提交于
The bus and architecture dependencies are already on MFD_CS5535, so there is no need to repeat them here. Signed-off-by: NJean Delvare <jdelvare@suse.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 07 3月, 2014 1 次提交
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由 Alan Tull 提交于
fix build error with this message: kernel/irq/Kconfig:41:error: recursive dependency detected! kernel/irq/Kconfig:41: symbol GENERIC_IRQ_CHIP is selected by GPIO_DWAPB drivers/gpio/Kconfig:131: symbol GPIO_DWAPB depends on IRQ_DOMAIN kernel/irq/Kconfig:46: symbol IRQ_DOMAIN is selected by GENERIC_IRQ_CHIP Signed-off-by: NAlan Tull <atull@altera.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 06 3月, 2014 1 次提交
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由 Linus Walleij 提交于
Instead of just depending on OF and getting build failures, depend on ARM && OF_GPIO. Cc: Fabian Vogt <fabian@ritter-vogt.de> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 05 3月, 2014 1 次提交
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由 Jamie Iles 提交于
The Synopsys DesignWare block is used in some ARM devices (picoxcell) and can be configured to provide multiple banks of GPIO pins. v12: - Add irq_startup/shutdown - do irq_create_mapping() in probe, irq_find_mapping() in to_irq() - Adjust mappings to show support for 1 gpio per port. - gpio-cells = <1> v11: - Use NULL when checking existence of 'interrupts' property - Bindings descriptions cleanup v10: - in documentation nr-gpio -> nr-gpios v9: - cleanup in dt bindings doc - use of_get_child_count() v8: - remove socfpga.dtsi changes - minor cleanup in devicetree documentation v7: - use irq_generic_chip - support one irq per gpio line or one irq for many - s/bank/port/ and other cleanup v6: - (atull) squash the set of patches - use linear irq domain - build fixes. Original driver was reviewed on v3.2. - Fix setting irq edge type for 'rising' and 'both'. - Support as a loadable module. - Use bgpio_chip's spinlock during register access. - Clean up register names to match spec - s/bank/port/ because register names use the word 'port' - s/nr-gpio/nr-gpios/ - don't get/put the of_node - remove signoffs/acked-by's because of changes - other cleanup v5: - handle sparse bank population correctly v3: - depend on rather than select IRQ_DOMAIN - split IRQ support into a separate patch v2: - use Rob Herring's irqdomain in generic irq chip patches - use reg property to indicate bank index - support irqs on both edges based on LinusW's u300 driver Signed-off-by: NJamie Iles <jamie@jamieiles.com> Signed-off-by: NAlan Tull <atull@altera.com> Reviewed-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 27 2月, 2014 2 次提交
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由 Fabian Vogt 提交于
This driver supports the GPIO controller found in LSI ZEVIO SoCs. It has been successfully tested on a TI nspire CX calculator. Signed-off-by: NFabian Vogt <fabian@ritter-vogt.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jean Delvare 提交于
There is no point in displaying the TS5500-specific driver entries if TS5500 board support itself isn't enabled. Signed-off-by: NJean Delvare <jdelvare@suse.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Acked-by: NAlexandre Courbot <gnurou@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 25 2月, 2014 1 次提交
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由 Kumar Gala 提交于
We've split Qualcomm MSM support into legacy and multiplatform. The gpio msm-v2 driver is only relevant on the multiplatform supported SoCs so switch the Kconfig depends to ARCH_QCOM. CC: Linus Walleij <linus.walleij@linaro.org> Acked-by: NAlexandre Courbot <gnurou@gmail.com> Signed-off-by: NKumar Gala <galak@codeaurora.org>
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- 13 2月, 2014 3 次提交
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由 Aaron Sierra 提交于
Add Exar XRA1202 8-bit GPIO expander to supported list. Signed-off-by: NAaron Sierra <asierra@xes-inc.com> Acked-by: NGraeme Smecher <gsmecher@threespeedlogic.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Aaron Sierra 提交于
Add the NXP PCA9698 40-bit GPIO expander to the supported list. Note: This only enables GPIO functionality. Tested-by: NBob Schmitz <bschmitz@xes-inc.com> Signed-off-by: NAaron Sierra <asierra@xes-inc.com> Acked-by: NGraeme Smecher <gsmecher@threespeedlogic.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Aaron Sierra 提交于
The pca953x driver supports tca6424 (24-bit) and pca9505 (40-bit) devices. They were the only supported devices not mentioned in the Kconfig help. Signed-off-by: NAaron Sierra <asierra@xes-inc.com> Acked-by: NGraeme Smecher <gsmecher@threespeedlogic.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 06 2月, 2014 1 次提交
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由 Axel Lin 提交于
commit f1f70479 "gpio: pl061: support irqdomain" drops the support of irq generic chip and use irqdomain instead. Thus fixes the dependency by selecting IRQ_DOMAIN rather than GENERIC_IRQ_CHIP. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 05 2月, 2014 1 次提交
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由 Axel Lin 提交于
gpio-tb10x driver uses generic irq chip APIs (irq_alloc_domain_generic_chips, irq_remove_generic_chip), so it needs to select GENERIC_IRQ_CHIP to avoid build error. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 1月, 2014 1 次提交
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由 Milo Kim 提交于
This is one of LP3943 MFD driver. LP3943 is configurable as a GPIO expander, up to 16 GPIOs. * Application note: how to configure LP3943 as a GPIO expander http://www.ti.com/lit/an/snva287a/snva287a.pdf * Supported GPIO controller operations request, free, direction_input, direction_output, get and set * GPIO direction register not supported LP3943 doesn't have the GPIO direction register. It only provides input and output status registers. So, private data for the direction should be handled manually. This variable is updated whenever the direction is changed and used in 'get' operation. * Pin assignment A driver data, 'pin_used' is checked when a GPIO is requested. If the GPIO is already assigned, then returns as failure. If the GPIO is available, 'pin_used' is set. When the GPIO is not used anymore, then it is cleared. It is defined as unsigned long type for atomic bit operation APIs, but only LSB 16bits are used because LP3943 has 16 outputs. Signed-off-by: NMilo Kim <milo.kim@ti.com> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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- 20 1月, 2014 1 次提交
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由 Linus Walleij 提交于
The MCP drivers fails to compile on trial builds due to missing Kconfig dependency on OF_GPIO. Fix it. Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 17 1月, 2014 1 次提交
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由 Lars Poeschel 提交于
This adds interrupt functionality for i2c chips to the driver. They can act as a interrupt-controller and generate interrupts, if the inputs change. This is tested with a mcp23017 chip on an arm based platform. v3: - be a bit more clear that the irq functionality is also available on spi versions of the chips, but the linux driver does not support this yet v2: - some more word about irq-mirror property in binding doc - use of_read_bool instead of of_find_property for "interrupt-contrller" and "irq-mirror" - cache the "interrupt-controller" for remove function - do set the irq-mirror bit only if device is marked as interrupt-controller - do create the irq mapping and setup of irq_desc of all possible interrupts in probe path instead of in gpio_to_irq - mark gpios as in use as interrupts in irq in irq_startup and unlock it in irq_shutdown - rename virq to child_irq - remove dev argument from mcp23s08_irq_setup function - move gpiochip_add before mcp23s08_irq_setup in probe path Signed-off-by: NLars Poeschel <poeschel@lemonage.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 08 1月, 2014 2 次提交
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由 Baruch Siach 提交于
Prevent build failure when the selected variant does not support GPIO32. Acked-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Alexander Shiyan 提交于
This helps increasing build testing coverage. Signed-off-by: NAlexander Shiyan <shc_work@mail.ru> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 26 12月, 2013 1 次提交
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由 Grygorii Strashko 提交于
The compatible to Davinci GPIO HW block is used by other TI SoCs, like Keystone, where GPIO support is declared as optional. Hence, introduce GPIO_DAVINCI Kconfig option which will allow to enable Davinci GPIO driver for Keystone SoCs when needed. At same time, kept Davinci GPIO driver enabled for Davinci SoCs by default. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NLad, Prabhakar <prabhakar.csengg@gmail.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com>
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- 20 12月, 2013 1 次提交
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由 Bruno Randolf 提交于
This patch adds support for the GPIOs found on the SMSC "Super I/ SCH311x. The chip detection and I/O functions are copied from sch311x_wdt. Signed-off-by: NBruno Randolf <br1@einfach.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 12 12月, 2013 2 次提交
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由 Baruch Siach 提交于
GPIO32 is a standard optional extension to the Xtensa architecture core that provides preconfigured output and input ports for intra SoC signaling. The GPIO32 option is implemented as 32bit Tensilica Instruction Extension (TIE) output state called EXPSTATE, and 32bit input wire called IMPWIRE. This driver treats input and output states as two distinct devices. v3: * Use BUG() in xtensa_impwire_set_value() to indicate that it should never be called (Linus Walleij) v2: * Address the comments of Linus Walleij: - Add a few comments - Expand commit log message - Use the BIT() macro for bit offsets - Rewrite CPENABLE handling as static inlines - Use device_initcall() * Depend on !SMP for reason explained in the comments (Marc Gauthier) * Use XCHAL_CP_ID_XTIOP to enable/disable GPIO32 only Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Alexander Shiyan 提交于
Commit 20bc4d5d (gpio: 74x164: Add support for the daisy-chaining) introduce check for DT for the driver, so driver cannot be used without DT. There are no in-tree users of this driver, so remove non-DT support completely. Signed-off-by: NAlexander Shiyan <shc_work@mail.ru> Acked-by: NMark Brown <broonie@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 03 12月, 2013 2 次提交
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由 Jonas Jensen 提交于
Add GPIO driver for MOXA ART SoCs. Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jean Delvare 提交于
Change CONFIG_GPIO_LYNXPOINT from bool to tristate so that the gpio-lynxpoint driver can be built as a module. Add the required glue: an exit function to unregister the driver, and module information. Signed-off-by: NJean Delvare <jdelvare@suse.de> Cc: Mathias Nyman <mathias.nyman@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 06 11月, 2013 1 次提交
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由 Rob Herring 提交于
The pl061 driver has no real dependency on ARM, so remove the kconfig dependency. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 30 10月, 2013 1 次提交
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由 Alexandre Courbot 提交于
Current Kconfig allows GPIO_DEVRES to be selected and compiled without GPIOLIB. This does not make sense anymore since GPIOLIB has become the exclusive way to deal with GPIOs. This patch makes GPIO_DEVRES available only if GPIOLIB is selected. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 26 10月, 2013 1 次提交
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由 Christian Ruppert 提交于
The GPIO driver for the Abilis Systems TB10x series of SOCs based on ARC700 CPUs. It supports GPIO control and GPIO interrupt generation. This driver works in conjunction with the TB10x pinctrl driver. Signed-off-by: NSascha Leuenberger <sascha.leuenberger@abilis.com> Signed-off-by: NChristian Ruppert <christian.ruppert@abilis.com> Acked-by: NKumar Gala <galak@codeaurora.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 11 10月, 2013 1 次提交
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由 David Cohen 提交于
gpio-langwell is a deprecated name. Despite the driver was made initially for Langwell, it supports now other Intel Mid SoC's. This patch does no change beside the file renaming with Kconfig/Makefile update. Signed-off-by: NDavid Cohen <david.a.cohen@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 9月, 2013 3 次提交
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由 Linus Walleij 提交于
Move the IOP GPIO driver to live with its siblings in the GPIO subsystem. Cc: Lennert Buytenhek <kernel@wantstofly.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Mikael Pettersson <mikpe@it.uu.se> Tested-by: NAaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jean Delvare 提交于
With the recent code cleanup from Marek Vasut, driver gpio-ucb1400 can be built as a module, so change symbol GPIO_UCB1400 from bool to tristate. Signed-off-by: NJean Delvare <jdelvare@suse.de> Reviewed-by: NMarek Vasut <marex@denx.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Markus Mayer 提交于
Add the GPIO driver for the Broadcom bcm281xx family of mobile SoCs. These GPIO controllers may contain up to 8 banks where each bank includes 32 pins that can be driven high or low and act as an edge sensitive interrupt. Signed-off-by: NMarkus Mayer <markus.mayer@linaro.org> Reviewed-by: NChristian Daudt <csd@broadcom.com> Reviewed-by: NTim Kryger <tim.kryger@linaro.org> Reviewed-by: NMatt Porter <matt.porter@linaro.org> Reviewed-by: NStephen Warren <swarren@nvidia.com> [Added depends on OF_GPIO] Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 19 9月, 2013 1 次提交
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由 Ian Molton 提交于
EMEV2 is now a DT platform, however the GPIO driver cannot be used from a DT file since it does not fill out the of_node field in its gpio_chip structure. Signed-off-by: NIan Molton <ian.molton@codethink.co.uk> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 13 9月, 2013 1 次提交
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由 Martin Schwidefsky 提交于
After the last architecture switched to generic hard irqs the config options HAVE_GENERIC_HARDIRQS & GENERIC_HARDIRQS and the related code for !CONFIG_GENERIC_HARDIRQS can be removed. Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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- 30 8月, 2013 1 次提交
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由 Simon Guinot 提交于
This patch adds support for the GPIOs found on the Fintek super-I/O chips F71882FG and F71889F. A super-I/O is a legacy I/O controller embedded on x86 motherboards. It is used to connect the low-bandwidth devices. Among others functions the F71882FG/F71889F provides: a parallel port, two serial ports, a keyboard controller, an hardware monitoring controller and some GPIO pins. Note that this super-I/Os are embedded on some Atom-based LaCie NASes. The GPIOs are used to control the LEDs and the hard drive power. Changes since v3: - Use request_muxed_region to protect the I/O ports against concurrent accesses. Changes since v2: - Remove useless NULL setters for driver data. Changes since v1: - Enhance the commit message by describing what is a Super-I/O. - Use self-explanatory names for the GPIO register macros. - Add a comment to explain the platform device and driver registration. - Fix gpio_get when GPIO is configured in input mode. I only had the hardware to check this mode recently... Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 26 8月, 2013 1 次提交
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由 David Daney 提交于
The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip GPIO pins, this driver handles them all. Configuring the pins as interrupt sources is handled elsewhere (OCTEON's irq handling code). Signed-off-by: NDavid Daney <david.daney@cavium.com> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5633/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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