1. 02 6月, 2017 2 次提交
  2. 11 4月, 2017 1 次提交
  3. 07 2月, 2017 1 次提交
  4. 16 9月, 2016 1 次提交
  5. 01 7月, 2016 1 次提交
    • S
      iwlwifi: pcie: workaround HW shadow registers bug · 1316d595
      Sara Sharon 提交于
      Integrated 9000 devices have a bug with shadow registers
      value retention.
      If driver writes RBD registers while MAC is asleep the
      values are stored in shadow registers to be copied whenever
      MAC wakes up.
      However, in 9000 devices a MAC wakeup is not triggered
      and when the bus powers down due to inactivity the shadow
      values and dirty bits are lost.
      Turn on the chicken-bits that cause MAC wakeup for RX-related
      values as well when the device is in D0.
      When the device is in low power mode turn the RX wakeup chicken
      bits off since driver is idle and this W/A is not needed.
      Remove previous W/A which was ineffective.
      Signed-off-by: NSara Sharon <sara.sharon@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      1316d595
  6. 11 5月, 2016 1 次提交
  7. 10 3月, 2016 1 次提交
  8. 28 2月, 2016 1 次提交
  9. 20 12月, 2015 1 次提交
  10. 18 11月, 2015 1 次提交
  11. 05 8月, 2015 1 次提交
    • M
      iwlwifi: mvm: Add FW paging mechanism for the UMAC on SDIO · e1120187
      Matti Gottlieb 提交于
      Family 8000 products has 2 embedded processors, the first
      known as LMAC (lower MAC) and implements the functionality from
      previous products, the second one is known as UMAC (upper MAC)
      and is used mainly for driver offloads as well as new features.
      The UMAC is typically “less” real-time than the LMAC and is used
      for higher level controls.
      The UMAC's code/data size is estimated to be in the mega-byte arena,
      taking into account the code it needs to replace in the driver and
      the set of new features.
      
      In order to allow the UMAC to execute code that is bigger than its code
      memory, we allow the UMAC embedded processor to page out code pages on
      DRAM.
      
      When the device is slave on the bus(SDIO) the driver saves the UMAC's
      image pages in blocks of 32K in the DRAM and sends the layout of the
      pages to the FW. When the FW wants load / unload pages, it creates an
      interrupt,	and the driver uploads / downloads the page to an address in
      the a specific address on the device's memory.
      
      The driver can support up to 1 MB of pages.
      
      Add paging mechanism for the UMAC on SDIO in order to allow the program to
      use a larger virtual space while using less physical memory on the device
      itself.
      Signed-off-by: NMatti Gottlieb <matti.gottlieb@intel.com>
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      e1120187
  12. 04 8月, 2015 1 次提交
  13. 22 1月, 2015 1 次提交
  14. 29 12月, 2014 1 次提交
  15. 24 11月, 2014 1 次提交
  16. 11 11月, 2014 1 次提交
  17. 14 9月, 2014 1 次提交
  18. 04 9月, 2014 1 次提交
  19. 10 3月, 2014 1 次提交
    • A
      iwlwifi: pcie: enable LP XTAL to reduce power consumption · a812cba9
      Alexander Bondar 提交于
      1. Enable LP XTAL to avoid HW bug where device may consume much
      power if FW is not loaded after device reset. LP XTAL is
      disabled by default after device HW reset. Configure device's
      "persistence" mode to avoid resetting XTAL again when SHRD_HW_RST
      occurs in S3.
      
      2. Add methods to access SHR (shared block memory space) directly from PCI
      bus w/o need to power up MAC HW.
      
      Shared internal registers (e.g. SHR_APMG_GP1, SHR_APMG_XTAL_CFG)can be
      accessed directly from PCI bus through SHR arbiter even when MAC HW is
      powered down. This is possible due to indirect read/write via
      HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and HEEP_CTRL_WRD_PCIEX_DATA (0xF4)
      registers.
      
      Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
      need not be powered up so no "grab inc access" is required.
      
      For example, to read from SHR_APMG_GP1 register (0x1DC),
      first, write to the control register:
      HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
      HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
      second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
      
      To write the register, first, write to the data register
      HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
      HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
      HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
      Signed-off-by: NAlexander Bondar <alexander.bondar@intel.com>
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      a812cba9
  20. 04 2月, 2014 1 次提交
  21. 01 1月, 2014 1 次提交
  22. 18 12月, 2013 1 次提交
  23. 26 11月, 2013 1 次提交
    • E
      iwlwifi: pcie: fix interrupt coalescing for 7260 / 3160 · 6960a059
      Emmanuel Grumbach 提交于
      We changed the timeout for the interrupt coealescing for
      calibration, but that wasn't effective since we changed
      that value back before loading the firmware. Since
      calibrations are notification from firmware and not Rx
      packets, this doesn't change anyway - the firmware will
      fire an interrupt straight away regardless of the interrupt
      coalescing value.
      Also, a HW issue has been discovered in 7000 devices series.
      The work around is to disable the new interrupt coalescing
      timeout feature - do this by setting bit 31 in
      CSR_INT_COALESCING.
      This has been fixed in 7265 which means that we can't rely
      on the device family and must have a hint in the iwl_cfg
      structure.
      
      Cc: stable@vger.kernel.org [3.10+]
      Fixes: 99cd4714 ("iwlwifi: add 7000 series device configuration")
      Reviewed-by: NJohannes Berg <johannes.berg@intel.com>
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      6960a059
  24. 11 10月, 2013 1 次提交
  25. 29 5月, 2013 1 次提交
  26. 06 3月, 2013 1 次提交
  27. 24 1月, 2013 1 次提交
  28. 03 1月, 2013 1 次提交
  29. 06 6月, 2012 2 次提交
  30. 17 4月, 2012 1 次提交
  31. 25 1月, 2012 1 次提交
  32. 07 1月, 2012 1 次提交
  33. 09 11月, 2011 1 次提交
  34. 15 9月, 2011 1 次提交
  35. 21 7月, 2011 1 次提交
  36. 08 4月, 2011 1 次提交
  37. 25 3月, 2011 1 次提交
  38. 01 2月, 2011 1 次提交
    • W
      iwlagn: add IQ inversion support for 2000 series devices · 52e6b85f
      Wey-Yi Guy 提交于
      The I/Q swapping is extremely important and should be dealt with extra care.
      It will affects OFDM and CCK differently.
      
      For 6000/6005/6030 series devices, the I/Q were swapped, and for 2000 series
      devices, it is in non-swapped status (but its swapped with respected to 6000/6005/6030).
      so the CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER register need to be set to support
      the correct behavior.
      Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
      52e6b85f