- 02 6月, 2017 2 次提交
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由 Haim Dreyfuss 提交于
Integrated chip may have different HW and RF steps. Currently, the driver supports only different HW steps. Add logic to support different RF steps enables combining different HW and RF steps. Signed-off-by: NHaim Dreyfuss <haim.dreyfuss@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
Three configurations will share device ID 2720, and will be differentiated by RF ID. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 11 4月, 2017 1 次提交
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由 Luca Coelho 提交于
One of the RF modules we support has been deprecated and never released publicly. Remove support for this module. Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 07 2月, 2017 1 次提交
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由 Sara Sharon 提交于
Support differentiating between two phys for a000 devices in order to load the correct firmware. Eventually when moving completely to the new phy we will be able to remove this. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 16 9月, 2016 1 次提交
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由 Haim Dreyfuss 提交于
In case the OS provides fewer interrupts than requested, different causes will share the same interrupt vector as follow: 1.One interrupt less: non rx causes shared with FBQ. 2.Two interrupts less: non rx causes shared with FBQ and RSS. 3.More than two interrupts: we will use fewer RSS queues. Also make the request depend on the number of online CPUs instead of possible CPUs. Signed-off-by: NHaim Dreyfuss <haim.dreyfuss@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 01 7月, 2016 1 次提交
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由 Sara Sharon 提交于
Integrated 9000 devices have a bug with shadow registers value retention. If driver writes RBD registers while MAC is asleep the values are stored in shadow registers to be copied whenever MAC wakes up. However, in 9000 devices a MAC wakeup is not triggered and when the bus powers down due to inactivity the shadow values and dirty bits are lost. Turn on the chicken-bits that cause MAC wakeup for RX-related values as well when the device is in D0. When the device is in low power mode turn the RX wakeup chicken bits off since driver is idle and this W/A is not needed. Remove previous W/A which was ineffective. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 11 5月, 2016 1 次提交
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由 Haim Dreyfuss 提交于
Currently there is one to one function between device id to it's ucode. The new generation devices allows to combine different phy and mac images. Now we have two different ucode images with the same device id. Read RF ID to identify phy image and overwrite it if needed. Signed-off-by: NHaim Dreyfuss <haim.dreyfuss@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 10 3月, 2016 1 次提交
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由 Sara Sharon 提交于
From 9000 family on, we need to get HW address from host CSR registers. OEM can override it by fusing the override registers - read those first, and if those are 0 - read the OTP registers instead. In addition - bail out if no valid mac address is present. Make it shared for all NICs. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 28 2月, 2016 1 次提交
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由 Haim Dreyfuss 提交于
Working with MSIX requires prior configuration. This includes requesting interrupt vectors from the OS, registering the vectors and mapping the optional causes to the relevant interrupt. In addition add new interrupt handler to handle MSIX interrupt. Signed-off-by: NHaim Dreyfuss <haim.dreyfuss@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 20 12月, 2015 1 次提交
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由 Emmanuel Grumbach 提交于
ilw@linux.intel.com is not available anymore. linuxwifi@intel.com should be used instead. Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 18 11月, 2015 1 次提交
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由 Kalle Valo 提交于
Part of reorganising wireless drivers directory and Kconfig. Signed-off-by: NKalle Valo <kvalo@codeaurora.org>
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- 05 8月, 2015 1 次提交
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由 Matti Gottlieb 提交于
Family 8000 products has 2 embedded processors, the first known as LMAC (lower MAC) and implements the functionality from previous products, the second one is known as UMAC (upper MAC) and is used mainly for driver offloads as well as new features. The UMAC is typically “less” real-time than the LMAC and is used for higher level controls. The UMAC's code/data size is estimated to be in the mega-byte arena, taking into account the code it needs to replace in the driver and the set of new features. In order to allow the UMAC to execute code that is bigger than its code memory, we allow the UMAC embedded processor to page out code pages on DRAM. When the device is slave on the bus(SDIO) the driver saves the UMAC's image pages in blocks of 32K in the DRAM and sends the layout of the pages to the FW. When the FW wants load / unload pages, it creates an interrupt, and the driver uploads / downloads the page to an address in the a specific address on the device's memory. The driver can support up to 1 MB of pages. Add paging mechanism for the UMAC on SDIO in order to allow the program to use a larger virtual space while using less physical memory on the device itself. Signed-off-by: NMatti Gottlieb <matti.gottlieb@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 04 8月, 2015 1 次提交
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由 Eliad Peller 提交于
Since the CSR_DRAM_INIT_TBL_WRITE_POINTER bit wasn't set on ict reset, in some flows (like disable ict followed by immediate reset ict) the driver and hardware went out of sync (the driver cleared the ict_index, while the hw kept it intact). Fix it by setting the flag when resetting ict. Signed-off-by: NEliad Peller <eliad@wizery.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 22 1月, 2015 1 次提交
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由 Eran Harary 提交于
C step functionality in the driver is exactly the same as B step besides the ucode name that present as iwlwifi-8000C-xx.ucode instead of iwlwifi-8000B-xx.ucode Signed-off-by: NEran Harary <eran.harary@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 29 12月, 2014 1 次提交
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由 Emmanuel Grumbach 提交于
When the driver is unload, the Manageability Engine should know about that - send an event to inform it about this event. Reviewed-by: NReuven Borok <reuven.borok@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 24 11月, 2014 1 次提交
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由 Johannes Berg 提交于
Identify 7265-D devices using the hardware revision (they have the same PCI IDs as 7265) and change the configuration for them taking the differences (currently only the firmware image) into account. Signed-off-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 11 11月, 2014 1 次提交
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由 Emmanuel Grumbach 提交于
This is fully backward compatible with older platforms. Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 14 9月, 2014 1 次提交
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由 Liad Kaufman 提交于
Rather than ANDing with a mask - use existing macros, which are more readable. Signed-off-by: NLiad Kaufman <liad.kaufman@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 04 9月, 2014 1 次提交
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由 Johannes Berg 提交于
Our legal structure changed at some point (see wikipedia), but we forgot to immediately switch over to the new copyright notice. For files that we have modified in the time since the change, add the proper copyright notice now. Signed-off-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 10 3月, 2014 1 次提交
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由 Alexander Bondar 提交于
1. Enable LP XTAL to avoid HW bug where device may consume much power if FW is not loaded after device reset. LP XTAL is disabled by default after device HW reset. Configure device's "persistence" mode to avoid resetting XTAL again when SHRD_HW_RST occurs in S3. 2. Add methods to access SHR (shared block memory space) directly from PCI bus w/o need to power up MAC HW. Shared internal registers (e.g. SHR_APMG_GP1, SHR_APMG_XTAL_CFG)can be accessed directly from PCI bus through SHR arbiter even when MAC HW is powered down. This is possible due to indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW need not be powered up so no "grab inc access" is required. For example, to read from SHR_APMG_GP1 register (0x1DC), first, write to the control register: HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. To write the register, first, write to the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) Signed-off-by: NAlexander Bondar <alexander.bondar@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 04 2月, 2014 1 次提交
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由 Eran Harary 提交于
Also handle the bypass mode in which the second CPU doesn't interfere. Signed-off-by: NEran Harary <eran.harary@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 01 1月, 2014 1 次提交
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由 Emmanuel Grumbach 提交于
Happy new year! Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 18 12月, 2013 1 次提交
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由 Emmanuel Grumbach 提交于
Since iwl_trans_pcie_alloc_ict is called in the PCIe allocation code, we always set CSR_INT_BIT_RX_PERIODIC. Move that bit to the default list of interrupts we enable and simplify the code. Also use dma_zalloc_ and avoid to memset the memory afterwards. trans_pcie->ict_index is 0 since trans_pcie has just been kzalloced, remove the redundant assignment. Reviewed-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 26 11月, 2013 1 次提交
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由 Emmanuel Grumbach 提交于
We changed the timeout for the interrupt coealescing for calibration, but that wasn't effective since we changed that value back before loading the firmware. Since calibrations are notification from firmware and not Rx packets, this doesn't change anyway - the firmware will fire an interrupt straight away regardless of the interrupt coalescing value. Also, a HW issue has been discovered in 7000 devices series. The work around is to disable the new interrupt coalescing timeout feature - do this by setting bit 31 in CSR_INT_COALESCING. This has been fixed in 7265 which means that we can't rely on the device family and must have a hint in the iwl_cfg structure. Cc: stable@vger.kernel.org [3.10+] Fixes: 99cd4714 ("iwlwifi: add 7000 series device configuration") Reviewed-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 11 10月, 2013 1 次提交
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由 Eran Harary 提交于
Support Signed firmware based on code signing system (CSS) protocol and dual CPUs download, the code recognize if there are more than one CPU and if we need to operate the signed protocol according to the ucode binary image Signed-off-by: NEran Harary <eran.harary@intel.com> Reviewed-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
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- 29 5月, 2013 1 次提交
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由 Eytan Lifshitz 提交于
In order to avoid NIC destruction due to high temperature, CT kill will power down the NIC. To avoid this, thermal throttling will decrease throughput to prevent the NIC from reaching the temperature at which CT kill is performed. Signed-off-by: NEytan Lifshitz <eytan.lifshitz@intel.com> Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
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- 06 3月, 2013 1 次提交
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由 Emmanuel Grumbach 提交于
7000.c was released as GPL only by mistake: it should be dual licensed - GPL / BSD. The file that contains the license in the kernel is COPYING and not LICENSE.GPL. Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
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- 24 1月, 2013 1 次提交
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由 Johannes Berg 提交于
Update Copyright notices to 2013. Reviewed-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
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- 03 1月, 2013 1 次提交
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由 Eytan Lifshitz 提交于
Fix typo in the macro name and the wrong value. Signed-off-by: NEytan Lifshitz <eytan.lifshitz@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
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- 06 6月, 2012 2 次提交
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由 Emmanuel Grumbach 提交于
This was missing. Fix the mask of the REV_TYPE on the way. Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
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由 Emmanuel Grumbach 提交于
Johannes noticed this was completely messed up. We got confused between masks and bit position. Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
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- 17 4月, 2012 1 次提交
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由 Amit Beka 提交于
This register is used to enable some debug mechanisms. Signed-off-by: NAmit Beka <amit.beka@intel.com> Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
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- 25 1月, 2012 1 次提交
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由 Wey-Yi Guy 提交于
Update Copyright to 2012 Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 07 1月, 2012 1 次提交
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由 Wey-Yi Guy 提交于
Update Copyright to 2012 Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
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- 09 11月, 2011 1 次提交
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由 Wey-Yi Guy 提交于
Set the HW rev. for both 105 and 135 series Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 15 9月, 2011 1 次提交
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由 Emmanuel Grumbach 提交于
This reaches encapsulation for this file. In order to reach this: * move priv->valid_context to iwl_shared * move the last_rejected initialization to the upper layer * define a wrapper iwl_nic_config in the upper layer that calls to cfg->lib->ops->nic_config Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 21 7月, 2011 1 次提交
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由 Johannes Berg 提交于
Implement WoWLAN support in iwlagn. The device supports a number of wakeup triggers and can do GTK rekeying when asleep (if HW crypto is used). Unfortunately, we need to disconnect from the AP after resume since we can't yet get all the info out of the wowlan uCode to stay connected safely. Signed-off-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
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- 08 4月, 2011 1 次提交
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由 Wey-Yi Guy 提交于
Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
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- 25 3月, 2011 1 次提交
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由 Wey-Yi Guy 提交于
After driver split, remove the unused reference to 3945 and 4965 Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
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- 01 2月, 2011 1 次提交
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由 Wey-Yi Guy 提交于
The I/Q swapping is extremely important and should be dealt with extra care. It will affects OFDM and CCK differently. For 6000/6005/6030 series devices, the I/Q were swapped, and for 2000 series devices, it is in non-swapped status (but its swapped with respected to 6000/6005/6030). so the CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER register need to be set to support the correct behavior. Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
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