1. 02 2月, 2008 3 次提交
  2. 30 1月, 2008 2 次提交
    • A
      x86: don't disable TSC in any C states on AMD Fam10h · ddb25f9a
      Andi Kleen 提交于
      The ACPI code currently disables TSC use in any C2 and C3
      states. But the AMD Fam10h BKDG documents that the TSC
      will never stop in any C states when the CONSTANT_TSC bit is
      set. Make this disabling conditional on CONSTANT_TSC
      not set on AMD.
      
      I actually think this is true on Intel too for C2 states
      on CPUs with p-state invariant TSC, but this needs
      further discussions with Len to really confirm :-)
      
      So far it is only enabled on AMD.
      
      Cc: lenb@kernel.org
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      ddb25f9a
    • V
      x86: voluntary leave_mm before entering ACPI C3 · bde6f5f5
      Venki Pallipadi 提交于
      Aviod TLB flush IPIs during C3 states by voluntary leave_mm()
      before entering C3.
      
      The performance impact of TLB flush on C3 should not be significant with
      respect to C3 wakeup latency. Also, CPUs tend to flush TLB in hardware while in
      C3 anyways.
      
      On a 8 logical CPU system, running make -j2, the number of tlbflush IPIs goes
      down from 40 per second to ~ 0. Total number of interrupts during the run
      of this workload was ~1200 per second, which makes it ~3% savings in wakeups.
      
      There was no measurable performance or power impact however.
      
      [ akpm@linux-foundation.org: symbol export fixes. ]
      Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      bde6f5f5
  3. 25 1月, 2008 5 次提交
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