1. 19 8月, 2016 2 次提交
  2. 15 8月, 2016 2 次提交
  3. 05 8月, 2016 2 次提交
  4. 04 8月, 2016 4 次提交
  5. 04 7月, 2016 1 次提交
  6. 20 5月, 2016 1 次提交
  7. 15 2月, 2016 1 次提交
  8. 23 11月, 2015 1 次提交
    • C
      drm/i915: Mark uneven memory banks on gen4 desktop as unknown swizzling · 0b466dc2
      Chris Wilson 提交于
      We have varied reports of swizzling corruption on gen4 desktop, and
      confirmation that one at least is triggered by uneven memory banks
      (L-shaped memory). The implication is that the swizzling varies between
      the paired channels and the remainder of memory on the single channel. As
      the object then has unpredictable swizzling (it will vary depending on
      exact page allocation and may even change during the object's lifetime as
      the pages are replaced), we have to report to userspace that the swizzling
      is unknown.
      
      However, some existing userspace is buggy when it meets an unknown
      swizzling configuration and so we need to tell another white lie and
      mark the swizzling as NONE but report it as UNKNOWN through the extended
      get-tiling-ioctl. See
      
      commit 5eb3e5a5
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Sun Jun 28 09:19:26 2015 +0100
      
          drm/i915: Declare the swizzling unknown for L-shaped configurations
      
      for the previous example where we found that telling the truth to
      userspace just ends up in a world of hurt.
      
      Also since we don't truly know what the swizzling is on the pages, we
      need to keep them pinned to prevent swapping as the reports also
      suggest that some gen4 devices have previously undetected bit17
      swizzling.
      
      v2: Combine unknown + quirk patches to prevent userspace ever seeing
      unknown swizzling through the normal get-tiling-ioctl. Also use the same
      path for the existing uneven bank detection for mobile gen4.
      Reported-by: NMatti Hämäläinen <ccr@tnsp.org>
      Tested-by: NMatti Hämäläinen <ccr@tnsp.org>
      References: https://bugs.freedesktop.org/show_bug.cgi?id=90725Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Matti Hämäläinen <ccr@tnsp.org>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: stable@vger.kernel.org
      Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Link: http://patchwork.freedesktop.org/patch/msgid/1447927085-31726-1-git-send-email-chris@chris-wilson.co.ukSigned-off-by: NJani Nikula <jani.nikula@intel.com>
      0b466dc2
  9. 18 11月, 2015 1 次提交
    • V
      drm/i915: Type safe register read/write · f0f59a00
      Ville Syrjälä 提交于
      Make I915_READ and I915_WRITE more type safe by wrapping the register
      offset in a struct. This should eliminate most of the fumbles we've had
      with misplaced parens.
      
      This only takes care of normal mmio registers. We could extend the idea
      to other register types and define each with its own struct. That way
      you wouldn't be able to accidentally pass the wrong thing to a specific
      register access function.
      
      The gpio_reg setup is probably the ugliest thing left. But I figure I'd
      just leave it for now, and wait for some divine inspiration to strike
      before making it nice.
      
      As for the generated code, it's actually a bit better sometimes. Eg.
      looking at i915_irq_handler(), we can see the following change:
        lea    0x70024(%rdx,%rax,1),%r9d
        mov    $0x1,%edx
      - movslq %r9d,%r9
      - mov    %r9,%rsi
      - mov    %r9,-0x58(%rbp)
      - callq  *0xd8(%rbx)
      + mov    %r9d,%esi
      + mov    %r9d,-0x48(%rbp)
       callq  *0xd8(%rbx)
      
      So previously gcc thought the register offset might be signed and
      decided to sign extend it, just in case. The rest appears to be
      mostly just minor shuffling of instructions.
      
      v2: i915_mmio_reg_{offset,equal,valid}() helpers added
          s/_REG/_MMIO/ in the register defines
          mo more switch statements left to worry about
          ring_emit stuff got sorted in a prep patch
          cmd parser, lrc context and w/a batch buildup also in prep patch
          vgpu stuff cleaned up and moved to a prep patch
          all other unrelated changes split out
      v3: Rebased due to BXT DSI/BLC, MOCS, etc.
      v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
      f0f59a00
  10. 30 9月, 2015 2 次提交
  11. 15 8月, 2015 1 次提交
    • M
      drm/i915/gtt: Allow >= 4GB offsets in X86_32 · 088e0df4
      Michel Thierry 提交于
      Similar to commit c44ef60e ("drm/i915/gtt:
      Allow >= 4GB sizes for vm"), i915_gem_obj_offset and i915_gem_obj_ggtt_offset
      return an unsigned long, which in only 4-bytes long in 32-bit kernels.
      
      Change return type (and other related offset variables) to u64.
      
      Since Global GTT is always limited to 4GB, this change would not be required
      in i915_gem_obj_ggtt_offset, but this is done for consistency.
      
      v2: Remove unnecessary offset variable in do_pin, as we already have
          vma->node.start (Chris).
          Update GGTT offset too (Tvrtko).
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Signed-off-by: NMichel Thierry <michel.thierry@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      088e0df4
  12. 27 7月, 2015 4 次提交