Use BT601 for SD/ED resolution and BT709 for HD resolution
Signed-off-by: NBich Hemon <bich.hemon@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

Atomic update should never fail. Thus all checks must be done in
the atomic_check function for each plane (gdp, hqvdp and cursor).
Signed-off-by: NVincent Abriou <vincent.abriou@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>

It may happen that the cursor is displayed with wrong colors which can
be explained by a CLUT wrongly fetched at the first display.
Fetching the CLUT at each commit (=move) ensures that the right colors
are used, at least from the first cursor move.
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

GDP source width should be equal to the destination width to get
rid of this issue.
Signed-off-by: NVincent Abriou <vincent.abriou@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>

When a GDP gets a scale request (which it does not support), it accepts it
but crops or clamps and outputs a warning message.
Signed-off-by: NBich Hemon <bich.hemon@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

Only RGB formats supported by GDP planes
Signed-off-by: NBich Hemon <bich.hemon@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

When a frame or a field is skipped, output a Warning message instead of
an Error message.
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

data_en is a local variable that doesn't need to be set as
awg_generate_instr can be called directly with the requested value.
Signed-off-by: NBich Hemon <bich.hemon@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

This update eases to understand the VTG programming.
It also sets a VTG output id for each supported connectors.
Signed-off-by: NVincent Abriou <vincent.abriou@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>

sti now support of atomic modesetting so set the flag to enable it.
Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

fix x/y typo while setting cursor coordinates
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Reviewed-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

Set CRTC modesetting parameters to avoid warnings in atomic mode.
Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

In some cases last_close() could be called before sti_gdp_disable()
and make kernel crash because mixer structure has been destroy.
Let's gdp keep a reference on vtg to fix that (like it is already done
in HQVDP)
Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for
Vybrid) whereas the register enumeration start from 1 (1-10 for
LS1021a and 1-9 for Vybrid). The loop started off from 0 for both
iterations and initialized the number of layers inclusive, which
is one layer too many.

All extensively written registers seem to be unassigned, it seems
that the write to those registers did not do any harm in practice.
Signed-off-by: NStefan Agner <stefan@agner.ch>

The current default configuration is as follows:
- Invert VSYNC signal (active LOW)
- Invert HSYNC signal (active LOW)

The mode flags allow to specify the required polarity per
mode. Furthermore, none of the current driver settings is
actually a standard polarity.

This patch applies the current driver default polarities as
explicit flags to the display which has been introduced with
the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now
also parses the flags field and applies the configuration
accordingly, by using the following values as standard
polarities: (e.g. when no flags are specified):
- VSYNC signal not inverted (active HIGH)
- HSYNC signal not inverted (active HIGH)
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>

Fix alpha blending by enabling alpha blending for the whole frame if
a color mode with alpha channel is selected (DRM_FORMAT_ARGB*). Also
support color modes without alpha channel (DRM_FORMAT_XRGB*) by just
not enabling alpha blending on layer level.
Signed-off-by: NStefan Agner <stefan@agner.ch>

The state of the interrupt mask register on initialization is
unknown, e.g. U-Boot could already used the DCU. So depending on
the boot loader, the outcome of the interrupt mask register could
be different. A defined state is much more preferable. Also, there
is no value in keeping interrupts enabled which we don't need.
Therefor, mask all interrupts on initialization.
Signed-off-by: NStefan Agner <stefan@agner.ch>

If initialization fails (e.g. due to missing panel node or deferred
probe) make sure to roll-back all operations and return the error
code.
Signed-off-by: NStefan Agner <stefan@agner.ch>

Improve error handling during CRTC initialization. Especially avoid
memory leaks in the primary plane initialization error path.
Signed-off-by: NStefan Agner <stefan@agner.ch>

It is not common to do regmap return value checks, especially not
for memory mapped device. We can rule out most error returns since
the conditions are static and we know they are ok (e.g. offset
aligned to register stride). Also without proper error handling
they are not really valuable for the user. Hence remove most of
them.

The check in the interrupt handler is worth keeping since a
volatile register won't be readable in case register caching is
still enabled.
Signed-off-by: NStefan Agner <stefan@agner.ch>

Since we are using cached registers, we need to specify volatile
registers explicitly to avoid reading their value from the cache.
This allows to read the correct interrupt status in fsl_dcu_drm_irq
and clear the asserted bits only.
Signed-off-by: NStefan Agner <stefan@agner.ch>

For state->fb or state->crtc may be NULL in fsl_dcu_drm_plane_atomic_check
function, if so, return 0.
Signed-off-by: NMeng Yi <meng.yi@nxp.com>
Signed-off-by: NJianwei Wang <jianwei.wang.chn@gmail.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>

Those formats are supported on Gen3 only.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Print a message when the HDMI I2C slave encoder can't be found to help
debugging probe deferral issues.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The LVDS encoder differs slightly in Gen3 SoCs in its PLL configuration.
Add support for the Gen3 LVDS PLL parameters and startup procedure.
Signed-off-by: NKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The bit is named PLLON in the datasheet, rename it.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The frequency checks don't match the datasheet, fix them.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the duplicate code by a single central function.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Document the R8A7795-specific DT bindings and support them in the
driver. The HDMI and LVDS outputs are currently not supported.
Signed-off-by: NKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The ODDF signal, output by default on the ODDF pin, isn't used on any
board supported in the kernel. As the Gen3 Salvator-X board uses the
ODDF pin as a DISP signal, hardcode that configuration in the driver.

Use of the ODDF signal will be implemented later through proper DT-based
configuration of the DU pins.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The DE signal is currently configured to be identical to the DISP
signal and is used for the same purpose. To make it clearer that the
DISP pin outputs the DISP signal, select it explicitly.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The Gen3 R8A7795 DU has 4 CRTCs, support them all.
Signed-off-by: NKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

LVDS support depends on DRM_RCAR_DU which already depends on OF. Drop
the explicit dependency.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The R8A7795 SoC is ARM64-based and include a DU. Enable driver
compilation on ARM64.
Signed-off-by: NKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Use %tu instead of %u to print difference between pointers.
Signed-off-by: NKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

On R-Car Gen3 SoCs the DU lost its ability to access memory directly and
needs to work in conjunction with the VSP to do so. This commit handles
the VSP internally to hide it from the user.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The plane allocator is specific to DU planes and won't be used for
VSP-based planes, move it with the rest of the DU planes code where it
belongs.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Plane sources are configured by the VSPS bit in the PnDDCR4 register.
Although the datasheet states that the bit is updated during vertical
blanking, it seems that updates only occur when the DU group is held in
reset through the DSYSR.DRES bit. Restart the group if the source
changes.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Configure the plane source at plane setup time to source frames from
memory or from the VSP1.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The R8A7790 DU can source frames directly from the VSP1 devices VSPD0
and VSPD1. VSPD0 feeds DU0/1 plane 0, and VSPD1 feeds either DU2 plane 0
or DU0/1 plane 1.

Allocate the correct fixed plane when sourcing frames from VSPD0 or
VSPD1, and allocate planes in reverse index order otherwise to ensure
maximum availability of planes 0 and 1.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>