Use common of_clk_init() function for clocks initialization.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@gmail.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

AC97 controller clock is hardwired to pll_a_out0.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The USB clocks are just clock gates, so no need to set a specific clock.
In fact trying to set a specific clock is just a NOP if the requested
clockrate is the same as those of the parent (clk_m) or will trigger a
WARN_ON() if rates don't match up.

As we are not setting a specific rate, nor activating the clocks at
init, there is no point in keeping the the usb entries in the clock init
table.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.

The following changes were done:

* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
  by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.

The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.

To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.

gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Acked-by: NMike Turquette <mturquette@linaro.org>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Acked-By: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk.
Remove the clocks related to the divider.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Remove duplicate smp_twd clocks as these clocks are accessed using
DT now.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Initialise the parent of UARTs to PLLP and disabling clock by
default.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

enum tegra*_clk is intended to match the IDs listed in the Tegra clock
bindings. There are a few mismatches, which this patch fixes:

1) pll_s and cop were left out of the Tegra20 enum.

2) spdif_in and spdif_out were swapped relative to the Tegra30 binding.

3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added
   to the Tegra30 enum.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>

The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add Tegra20 clock support based on common clock framework.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe,
implemented KBC clock, ensure all OF lookups return valid cookies i.e.
an explicit error pointer or valid pointer not NULL, adapt to renames
in earlier patches, fixed some checkpatch issues.]
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>