- 20 10月, 2017 3 次提交
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由 Geert Uytterhoeven 提交于
Move R-Car H3 ES2.0 I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Geert Uytterhoeven 提交于
Move R-Car H3 ES2.0 bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 308 bytes. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Geert Uytterhoeven 提交于
On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of sh_pfc_{read,write}_reg() already operate on 32-bit registers only. Hence make the 32-bit width implicit, and rename the functions to sh_pfc_{read,write}() to shorten lines. All accesses to 8-bit or 16-bit registers are still done using sh_pfc_{read,write}_raw_reg(). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
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- 11 10月, 2017 3 次提交
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由 Wolfram Sang 提交于
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Wolfram Sang 提交于
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Geert Uytterhoeven 提交于
Add pins, groups, and a function for the INTC-EX interrupt controller on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 05 10月, 2017 1 次提交
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由 Geert Uytterhoeven 提交于
Move the SCIF_CLK pins where they belong. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 04 10月, 2017 3 次提交
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由 Wolfram Sang 提交于
Since pinmuxing for I2C is equal on H3 ES1.0 and later versions, copy the I2C settings from ES1.0. Fixes this error in upstream for Salvator-XS: sh-pfc e6060000.pin-controller: function 'i2c2' not supported sh-pfc e6060000.pin-controller: invalid function i2c2 in map table i2c-rcar: probe of e6510000.i2c failed with error -22 Now, the bus works the same as with other Salvator boards. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 02 10月, 2017 1 次提交
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由 Takeshi Kihara 提交于
This patch adds USB3.0 ch0 pinmux support to R8A7795 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 19 9月, 2017 2 次提交
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由 Dirk Behme 提交于
DRIF support for r8a7795 was initially added with commit 2d775831 ("pinctrl: sh-pfc: r8a7795: Add DRIF support") and later dropped from the new pfc-r8a7795.c while re-naming the initial pfc-r8a7795.c to pfc-r8a7795-es1.c in commit b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0"). As the DRIF doesn't differ, re-add it here. Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
Add SDHI0-3 support for R-Car H3 ES2.0 based on a patch from the Renesas BSP. SDHI pin config is identical to H3 ES1.*. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 16 8月, 2017 11 次提交
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由 Takeshi Kihara 提交于
This is a correction because MOD_SEL register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch renames the pin function macro definitions of the GPSR1 and IPSR4 registers value for the CS1# pin. This is a correction because GPSR and IPSR register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch fixes the macro definitions of FSCLKST pins function and IPSR7 bit[15:12] register deleted. This is a correction because IPSR register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E or later. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch fixes to set MOD_SEL2 bit19 when using TCLK2_A pin function is selected for IPSR16 bit[23:20] or using TCLK2_B pin function is selected for IPSR17 bit[27:24]. And renames MOD_SEL2 bit26 value definition name to SEL_TIMER_TMU1. This is a correction because MOD_SEL register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch fixes the implementation incorrect of IPSR register value definitions for NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch fixes the implementation incorrect of IPSR register value definitions for FMCLK{_C,_D} and FMIN{_C,_D} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1 bit11 to MOD_SEL1 bit10. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7795 ES2.0 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.53E or later. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch fixes the implementation incorrect of MOD_SEL2 bit26 value when SCK5_A pin function is selected for IPSR16 bit[31:28]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7795 ES2.0 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: 0b0ffc96 ("pinctrl: sh-pfc: Initial R8A7795 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Yoshihiro Shimoda 提交于
Add pins, groups, and functions for USB 2.0 on R-Car H3 ES2.0. Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Yoshihiro Shimoda 提交于
Since the latest datasheet revises the names, this patch changes the definitions from USB3_{OVC,PWEN} to USB2_CH3_{OVC,PWEN}. Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 17 7月, 2017 2 次提交
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由 Geert Uytterhoeven 提交于
Add pins, groups, and functions for MSIOF on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara, with corrections for MSIOF3 SS1_E/SS2_E pins and SS2_E mux. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Takeshi Kihara 提交于
This patch fixes the incorrect IPSR register value definitions for MSIOF3_{SS1,SS2}_E pin functions. This is a correction to the incorrect implementation of IPSR register pin assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Reword, update Fixes for upstream] Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 26 6月, 2017 1 次提交
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由 Laurent Pinchart 提交于
Add pinctrl support for the PWM[0-6] pins. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 16 6月, 2017 1 次提交
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由 Laurent Pinchart 提交于
The H3 ES1.x and H3 ES2.0 have identical pinmuxing for the parallel RGB output support. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 13 6月, 2017 1 次提交
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由 Geert Uytterhoeven 提交于
Add pins, groups, and a function for EtherAVB on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 16 5月, 2017 1 次提交
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由 Kuninori Morimoto 提交于
R-Car Gen3 is using SSI_{WS,SCK}349 instead of SSI_{WS,SCK}34. But, current code is based on old datasheet which had typo. This patch fixes this typo. Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 30 3月, 2017 3 次提交
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由 Geert Uytterhoeven 提交于
Add pins, groups, and a function for SCIF_CLK on R-Car H3 ES2.0. SCIF_CLK is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF serial ports. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
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由 Geert Uytterhoeven 提交于
Add pins, groups, and functions for all SCIF serial ports on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
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由 Geert Uytterhoeven 提交于
The Pin Function Controller module in the R-Car H3 ES2.0 differs from ES1.x in many ways. The goal is twofold: 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary for now, 2. Make it clear which code supports ES1.x, so it can easily be identified and removed later, when production SoCs are deemed ubiquitous. Hence this patch: 1. Extracts the support for R-Car H3 ES1.x into a separate file, as the differences are quite large, 2. Adds code for detecting the SoC revision at runtime using the new soc_device_match() API, and selecting pinctrl tables for the actual SoC revision, 3. Replaces the core register and bitfield definitions by their counterparts for R-Car H3 ES2.0. The addition of pins, groups, and functions for the various on-chip devices is left to subsequent patches. The R-Car H3 ES2.0 register and bitfield definitions were extracted from a patch in the BSP by Takeshi Kihara. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
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- 21 3月, 2017 2 次提交
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由 Geert Uytterhoeven 提交于
Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong positions. Restore sort order (alphabetically, per group). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Geert Uytterhoeven 提交于
Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[]. Fixes: a56069c4 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions") Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 27 12月, 2016 1 次提交
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由 Niklas Söderlund 提交于
There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the bias to be configured. Add those pins to the list of pins and to the bias configuration array. The pins can now be referred to in DT by function names and their bias setting set. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 16 11月, 2016 4 次提交
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由 Niklas Söderlund 提交于
Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other than QSPI, but their drive strength can be controlled. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Niklas Söderlund 提交于
Group the AVB pins into similar groups found in other sh-pfc drivers. The pins can not be muxed between functions other then AVB but their drive strength can be controlled. The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and is in use in DT. Therefore add the ADV_MDIO pin to the existing group instead of renaming it. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Niklas Söderlund 提交于
There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the drive-strength to be configured. Add those pins to the list of pins and to the drive-strength configuration registers. The pins can now be referred to in DT by function names and their drive-strength modified. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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由 Niklas Söderlund 提交于
There is a bug in the r8a7795 bias code where a WARN() is trigged anytime a pin from PUEN0/PUD0 is accessed. # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8 [..] Call trace: [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128 [<ffff0000081fe3bc>] seq_read+0x16c/0x420 [<ffff00000831a110>] full_proxy_read+0x58/0x88 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8 [<ffff0000081d8874>] vfs_read+0x84/0x148 [<ffff0000081d9d64>] SyS_read+0x44/0xa0 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4 This is due to the WARN() check if the reg field of the pullups struct is zero, and this should be 0 for pins controlled by the PUEN0/PUD0 registers since PU0 is defined as 0. Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Fixes: 56065524 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support") Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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