1. 14 6月, 2018 1 次提交
    • L
      Kbuild: rename CC_STACKPROTECTOR[_STRONG] config variables · 050e9baa
      Linus Torvalds 提交于
      The changes to automatically test for working stack protector compiler
      support in the Kconfig files removed the special STACKPROTECTOR_AUTO
      option that picked the strongest stack protector that the compiler
      supported.
      
      That was all a nice cleanup - it makes no sense to have the AUTO case
      now that the Kconfig phase can just determine the compiler support
      directly.
      
      HOWEVER.
      
      It also meant that doing "make oldconfig" would now _disable_ the strong
      stackprotector if you had AUTO enabled, because in a legacy config file,
      the sane stack protector configuration would look like
      
        CONFIG_HAVE_CC_STACKPROTECTOR=y
        # CONFIG_CC_STACKPROTECTOR_NONE is not set
        # CONFIG_CC_STACKPROTECTOR_REGULAR is not set
        # CONFIG_CC_STACKPROTECTOR_STRONG is not set
        CONFIG_CC_STACKPROTECTOR_AUTO=y
      
      and when you ran this through "make oldconfig" with the Kbuild changes,
      it would ask you about the regular CONFIG_CC_STACKPROTECTOR (that had
      been renamed from CONFIG_CC_STACKPROTECTOR_REGULAR to just
      CONFIG_CC_STACKPROTECTOR), but it would think that the STRONG version
      used to be disabled (because it was really enabled by AUTO), and would
      disable it in the new config, resulting in:
      
        CONFIG_HAVE_CC_STACKPROTECTOR=y
        CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
        CONFIG_CC_STACKPROTECTOR=y
        # CONFIG_CC_STACKPROTECTOR_STRONG is not set
        CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
      
      That's dangerously subtle - people could suddenly find themselves with
      the weaker stack protector setup without even realizing.
      
      The solution here is to just rename not just the old RECULAR stack
      protector option, but also the strong one.  This does that by just
      removing the CC_ prefix entirely for the user choices, because it really
      is not about the compiler support (the compiler support now instead
      automatially impacts _visibility_ of the options to users).
      
      This results in "make oldconfig" actually asking the user for their
      choice, so that we don't have any silent subtle security model changes.
      The end result would generally look like this:
      
        CONFIG_HAVE_CC_STACKPROTECTOR=y
        CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
        CONFIG_STACKPROTECTOR=y
        CONFIG_STACKPROTECTOR_STRONG=y
        CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
      
      where the "CC_" versions really are about internal compiler
      infrastructure, not the user selections.
      Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      050e9baa
  2. 24 5月, 2018 3 次提交
    • M
      MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs · c7e81462
      Maciej W. Rozycki 提交于
      Use 64-bit accesses for 64-bit floating-point general registers with
      PTRACE_PEEKUSR, removing the truncation of their upper halves in the
      FR=1 mode, caused by commit bbd426f5 ("MIPS: Simplify FP context
      access"), which inadvertently switched them to using 32-bit accesses.
      
      The PTRACE_POKEUSR side is fine as it's never been broken and continues
      using 64-bit accesses.
      
      Fixes: bbd426f5 ("MIPS: Simplify FP context access")
      Signed-off-by: NMaciej W. Rozycki <macro@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 3.15+
      Patchwork: https://patchwork.linux-mips.org/patch/19334/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      c7e81462
    • M
      MIPS: prctl: Disallow FRE without FR with PR_SET_FP_MODE requests · 28e4213d
      Maciej W. Rozycki 提交于
      Having PR_FP_MODE_FRE (i.e. Config5.FRE) set without PR_FP_MODE_FR (i.e.
      Status.FR) is not supported as the lone purpose of Config5.FRE is to
      emulate Status.FR=0 handling on FPU hardware that has Status.FR=1
      hardwired[1][2].  Also we do not handle this case elsewhere, and assume
      throughout our code that TIF_HYBRID_FPREGS and TIF_32BIT_FPREGS cannot
      be set both at once for a task, leading to inconsistent behaviour if
      this does happen.
      
      Return unsuccessfully then from prctl(2) PR_SET_FP_MODE calls requesting
      PR_FP_MODE_FRE to be set with PR_FP_MODE_FR clear.  This corresponds to
      modes allowed by `mips_set_personality_fp'.
      
      References:
      
      [1] "MIPS Architecture For Programmers, Vol. III: MIPS32 / microMIPS32
          Privileged Resource Architecture", Imagination Technologies,
          Document Number: MD00090, Revision 6.02, July 10, 2015, Table 9.69
          "Config5 Register Field Descriptions", p. 262
      
      [2] "MIPS Architecture For Programmers, Volume III: MIPS64 / microMIPS64
          Privileged Resource Architecture", Imagination Technologies,
          Document Number: MD00091, Revision 6.03, December 22, 2015, Table
          9.72 "Config5 Register Field Descriptions", p. 288
      
      Fixes: 9791554b ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS")
      Signed-off-by: NMaciej W. Rozycki <macro@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 4.0+
      Patchwork: https://patchwork.linux-mips.org/patch/19327/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      28e4213d
    • M
      MIPS: ptrace: Make FPU context layout comments match reality · d1157b10
      Maciej W. Rozycki 提交于
      Correct comments across ptrace(2) handlers about an FPU register context
      layout discrepancy between MIPS I and later ISAs, which was fixed with
      `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator
      changes."), the fix corrected with LMO commit 849fa7a50dff ("R3k FPU
      ptrace() handling fixes."), and then broken and fixed over and over
      again, until last time fixed with commit 80cbfad7 ("MIPS: Correct
      MIPS I FP context layout").
      
      NB running the GDB test suite for the relevant ABI/ISA and watching out
      for regressions is advisable when poking around ptrace(2).
      Signed-off-by: NMaciej W. Rozycki <macro@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/19326/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      d1157b10
  3. 17 5月, 2018 1 次提交
  4. 15 5月, 2018 8 次提交
    • M
      MIPS: perf: Fix perf with MT counting other threads · 84002c88
      Matt Redfearn 提交于
      When perf is used in non-system mode, i.e. without specifying CPUs to
      count on, check_and_calc_range falls into the case when it sets
      M_TC_EN_ALL in the counter config_base. This has the impact of always
      counting for all of the threads in a core, even when the user has not
      requested it. For example this can be seen with a test program which
      executes 30002 instructions and 10000 branches running on one VPE and a
      busy load on the other VPE in the core. Without this commit, the
      expected count is not returned:
      
      taskset 4 dd if=/dev/zero of=/dev/null count=100000 & taskset 8 perf
      stat -e instructions:u,branches:u ./test_prog
      
       Performance counter stats for './test_prog':
      
                  103235      instructions:u
                   17015      branches:u
      
      In order to fix this, remove check_and_calc_range entirely and perform
      all of the logic in mipsxx_pmu_enable_event. Since
      mipsxx_pmu_enable_event now requires the range of the event, ensure that
      it is set by mipspmu_perf_event_encode in the same circumstances as
      before (i.e. #ifdef CONFIG_MIPS_MT_SMP && num_possible_cpus() > 1).
      
      The logic of mipsxx_pmu_enable_event now becomes:
      If the CPU is a BMIPS5000, then use the special vpe_id() implementation
      to select which VPE to count.
      If the counter has a range greater than a single VPE, i.e. it is a
      core-wide counter, then ensure that the counter is set up to count
      events from all TCs (though, since this is true by definition, is this
      necessary? Just enabling a core-wide counter in the per-VPE case appears
      experimentally to return the same counts. This is left in for now as the
      logic was present before).
      If the event is set up to count a particular CPU (i.e. system mode),
      then the VPE ID of that CPU is used for the counter.
      Otherwise, the event should be counted on the CPU scheduling this thread
      (this was the critical bit missing from the previous implementation) so
      the VPE ID of this CPU is used for the counter.
      
      With this commit, the same test as before returns the counts expected:
      
      taskset 4 dd if=/dev/zero of=/dev/null count=100000 & taskset 8 perf
      stat -e instructions:u,branches:u ./test_prog
      
       Performance counter stats for './test_prog':
      
                   30002      instructions:u
                   10000      branches:u
      Signed-off-by: NMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/19138/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      84002c88
    • M
      MIPS: perf: Use correct VPE ID when setting up VPE tracing · 840a8b55
      Matt Redfearn 提交于
      There are a couple of FIXME's in the perf code which state that
      cpu_data[event->cpu].vpe_id reports 0 for both CPUs. This is no longer
      the case, since the vpe_id is used extensively by SMP CPS.
      
      VPE local counting gets around this by using smp_processor_id() instead.
      As it happens this does work correctly to count events on the right VPE,
      but relies on 2 assumptions:
      a) Always having 2 VPEs / core.
      b) The hardware only paying attention to the least significant bit of
      the PERFCTL.VPEID field.
      If either of these assumptions change then the incorrect VPEs events
      will be counted.
      
      Fix this by replacing smp_processor_id() with
      cpu_vpe_id(&current_cpu_data), in the vpe_id() macro, and pass vpe_id()
      to M_PERFCTL_VPEID() when setting up PERFCTL.VPEID. The FIXME's can also
      be removed since they no longer apply.
      Signed-off-by: NMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/19137/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      840a8b55
    • M
      MIPS: perf: More robustly probe for the presence of per-tc counters · 800fb712
      Matt Redfearn 提交于
      The presence of per TC performance counters is now detected by
      cpu-probe.c and indicated by MIPS_CPU_MT_PER_TC_PERF_COUNTERS in
      cpu_data. Switch detection of the feature to use this new flag rather
      than blindly testing the implementation specific config7 register with a
      magic number.
      Signed-off-by: NMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Maciej W. Rozycki <macro@mips.com>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: Robert Richter <rric@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: oprofile-list@lists.sf.net
      Patchwork: https://patchwork.linux-mips.org/patch/19142/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      800fb712
    • M
      MIPS: Probe for MIPS MT perf counters per TC · 8270ab48
      Matt Redfearn 提交于
      Processors implementing the MIPS MT ASE may have performance counters
      implemented per core or per TC. Processors implemented by MIPS
      Technologies signify presence per TC through a bit in the implementation
      specific Config7 register. Currently the code which probes for their
      presence blindly reads a magic number corresponding to this bit, despite
      it potentially having a different meaning in the CPU implementation.
      
      Since CPU features are generally detected by cpu-probe.c, perform the
      detection here instead. Introduce cpu_set_mt_per_tc_perf which checks
      the bit in config7 and call it from MIPS CPUs known to implement this
      bit and the MT ASE, specifically, the 34K, 1004K and interAptiv.
      
      Once the presence of the per-tc counter is indicated in cpu_data, tests
      for it can be updated to use this flag.
      Suggested-by: NJames Hogan <jhogan@kernel.org>
      Signed-off-by: NMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Matt Redfearn <matt.redfearn@mips.com>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: Maciej W. Rozycki <macro@mips.com>
      Cc: linux-mips@linux-mips.org>
      Patchwork: https://patchwork.linux-mips.org/patch/19136/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      8270ab48
    • C
      MIPS: VPE: Fix spelling mistake: "uneeded" -> "unneeded" · aae22f16
      Colin Ian King 提交于
      Trivial fix to spelling mistake in pr_warn message text.
      Signed-off-by: NColin Ian King <colin.king@canonical.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kernel-janitors@vger.kernel.org
      Signed-off-by: NJames Hogan <jhogan@kernel.org>
      aae22f16
    • B
      MIPS: Convert update_persistent_clock() to update_persistent_clock64() · f06e7aa4
      Baolin Wang 提交于
      Since struct timespec is not y2038 safe on 32bit machines, this patch
      converts update_persistent_clock() to update_persistent_clock64() using
      struct timespec64.
      
      The rtc_mips_set_time() and rtc_mips_set_mmss() interfaces were using
      'unsigned long' type that is not y2038 safe on 32bit machines, moreover
      there is only one platform implementing rtc_mips_set_time() and two
      platforms implementing rtc_mips_set_mmss(), so we can just make them each
      implement update_persistent_clock64() directly, to get that helper out
      of the common mips code by removing rtc_mips_set_time() and
      rtc_mips_set_mmss() interfaces.
      Signed-off-by: NBaolin Wang <baolin.wang@linaro.org>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: NJames Hogan <jhogan@kernel.org>
      f06e7aa4
    • M
      MIPS: Fix ptrace(2) PTRACE_PEEKUSR and PTRACE_POKEUSR accesses to o32 FGRs · 9a3a92cc
      Maciej W. Rozycki 提交于
      Check the TIF_32BIT_FPREGS task setting of the tracee rather than the
      tracer in determining the layout of floating-point general registers in
      the floating-point context, correcting access to odd-numbered registers
      for o32 tracees where the setting disagrees between the two processes.
      
      Fixes: 597ce172 ("MIPS: Support for 64-bit FP with O32 binaries")
      Signed-off-by: NMaciej W. Rozycki <macro@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 3.14+
      Signed-off-by: NJames Hogan <jhogan@kernel.org>
      9a3a92cc
    • M
      MIPS: ptrace: Expose FIR register through FP regset · 71e909c0
      Maciej W. Rozycki 提交于
      Correct commit 7aeb753b ("MIPS: Implement task_user_regset_view.")
      and expose the FIR register using the unused 4 bytes at the end of the
      NT_PRFPREG regset.  Without that register included clients cannot use
      the PTRACE_GETREGSET request to retrieve the complete FPU register set
      and have to resort to one of the older interfaces, either PTRACE_PEEKUSR
      or PTRACE_GETFPREGS, to retrieve the missing piece of data.  Also the
      register is irreversibly missing from core dumps.
      
      This register is architecturally hardwired and read-only so the write
      path does not matter.  Ignore data supplied on writes then.
      
      Fixes: 7aeb753b ("MIPS: Implement task_user_regset_view.")
      Signed-off-by: NJames Hogan <jhogan@kernel.org>
      Signed-off-by: NMaciej W. Rozycki <macro@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 3.13+
      Patchwork: https://patchwork.linux-mips.org/patch/19273/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      71e909c0
  5. 25 4月, 2018 1 次提交
    • E
      signal/mips: Use force_sig_fault where appropriate · f43a54a0
      Eric W. Biederman 提交于
      Filling in struct siginfo before calling force_sig_info a tedious and
      error prone process, where once in a great while the wrong fields
      are filled out, and siginfo has been inconsistently cleared.
      
      Simplify this process by using the helper force_sig_fault.  Which
      takes as a parameters all of the information it needs, ensures
      all of the fiddly bits of filling in struct siginfo are done properly
      and then calls force_sig_info.
      
      In short about a 5 line reduction in code for every time force_sig_info
      is called, which makes the calling function clearer.
      
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: James Hogan <jhogan@kernel.org>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: N"Eric W. Biederman" <ebiederm@xmission.com>
      f43a54a0
  6. 19 4月, 2018 1 次提交
    • D
      compat: Move compat_timespec/ timeval to compat_time.h · 0d55303c
      Deepa Dinamani 提交于
      All the current architecture specific defines for these
      are the same. Refactor these common defines to a common
      header file.
      
      The new common linux/compat_time.h is also useful as it
      will eventually be used to hold all the defines that
      are needed for compat time types that support non y2038
      safe types. New architectures need not have to define these
      new types as they will only use new y2038 safe syscalls.
      This file can be deleted after y2038 when we stop supporting
      non y2038 safe syscalls.
      
      The patch also requires an operation similar to:
      
      git grep "asm/compat\.h" | cut -d ":" -f 1 |  xargs -n 1 sed -i -e "s%asm/compat.h%linux/compat.h%g"
      
      Cc: acme@kernel.org
      Cc: benh@kernel.crashing.org
      Cc: borntraeger@de.ibm.com
      Cc: catalin.marinas@arm.com
      Cc: cmetcalf@mellanox.com
      Cc: cohuck@redhat.com
      Cc: davem@davemloft.net
      Cc: deller@gmx.de
      Cc: devel@driverdev.osuosl.org
      Cc: gerald.schaefer@de.ibm.com
      Cc: gregkh@linuxfoundation.org
      Cc: heiko.carstens@de.ibm.com
      Cc: hoeppner@linux.vnet.ibm.com
      Cc: hpa@zytor.com
      Cc: jejb@parisc-linux.org
      Cc: jwi@linux.vnet.ibm.com
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Cc: linux-parisc@vger.kernel.org
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: linux-s390@vger.kernel.org
      Cc: mark.rutland@arm.com
      Cc: mingo@redhat.com
      Cc: mpe@ellerman.id.au
      Cc: oberpar@linux.vnet.ibm.com
      Cc: oprofile-list@lists.sf.net
      Cc: paulus@samba.org
      Cc: peterz@infradead.org
      Cc: ralf@linux-mips.org
      Cc: rostedt@goodmis.org
      Cc: rric@kernel.org
      Cc: schwidefsky@de.ibm.com
      Cc: sebott@linux.vnet.ibm.com
      Cc: sparclinux@vger.kernel.org
      Cc: sth@linux.vnet.ibm.com
      Cc: ubraun@linux.vnet.ibm.com
      Cc: will.deacon@arm.com
      Cc: x86@kernel.org
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NDeepa Dinamani <deepa.kernel@gmail.com>
      Acked-by: NSteven Rostedt (VMware) <rostedt@goodmis.org>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: NJames Hogan <jhogan@kernel.org>
      Acked-by: NHelge Deller <deller@gmx.de>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      0d55303c
  7. 03 4月, 2018 8 次提交
  8. 20 3月, 2018 1 次提交
  9. 17 3月, 2018 1 次提交
  10. 16 3月, 2018 1 次提交
  11. 12 3月, 2018 1 次提交
    • P
      perf/core: Remove perf_event::group_entry · 8343aae6
      Peter Zijlstra 提交于
      Now that all the grouping is done with RB trees, we no longer need
      group_entry and can replace the whole thing with sibling_list.
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Alexey Budankov <alexey.budankov@linux.intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: David Carrillo-Cisneros <davidcc@google.com>
      Cc: Dmitri Prokhorov <Dmitry.Prohorov@intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Kan Liang <kan.liang@intel.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Valery Cherepennikov <valery.cherepennikov@intel.com>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Cc: linux-kernel@vger.kernel.org
      Signed-off-by: NIngo Molnar <mingo@kernel.org>
      8343aae6
  12. 09 3月, 2018 2 次提交
    • M
      MIPS: pm-cps: Block system suspend when a JTAG probe is present · b2ed33a8
      Matt Redfearn 提交于
      If a JTAG probe is connected to a MIPS cluster, then the CPC detects it
      and latches the CPC.STAT_CONF.EJTAG_PROBE bit to 1. While set,
      attempting to send a power-down command to a core will be blocked, and
      the CPC will instead send the core to clock-off state. This can
      interfere with systems fully entering a low power state where all cores,
      CM, GIC, etc are powered down.
      
      Detect that a JTAG probe is / has been connected to the cluster and
      block the suspend attempt.
      
      Attempting to suspend the system while a JTAG probe is connected now
      yields:
       # echo mem > /sys/power/state
       [   11.654000] PM: Syncing filesystems ... done.
       [   11.658000] JTAG probe is connected - abort suspend
       -sh: echo: write error: Operation not permitted
       #
      
      To restore suspend, the JTAG probe should be disconnected or put into
      quiescent state. Platform code can then clear the
      CPC.STAT_CONF.EJTAG_PROBE bit.
      Reported-by: NEd Blake <ed.blake@sondrel.com>
      Signed-off-by: NMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/18641/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      b2ed33a8
    • P
      MIPS: Hang more efficiently on halt/powerdown/restart · 997e93d4
      Paul Burton 提交于
      The generic MIPS implementations of halting, powering down or restarting
      the system all hang using a busy loop as a last resort. We have many
      platforms which avoid this loop by implementing their own, many using
      some variation upon executing a wait instruction to lower CPU power
      usage if we reach this point.
      
      In order to prepare for cleaning up these various custom implementations
      of the same thing, this patch makes the generic machine_halt(),
      machine_power_off() & machine_restart() functions each make use of the
      wait instruction to lower CPU power usage in cases where we know that
      the wait instruction is available. If wait isn't known to be supported
      then we fall back to calling cpu_wait(), and if we don't have a
      cpu_wait() callback then we effectively continue using a busy loop.
      
      In effect the new machine_hang() function provides a superset of the
      functionality that the various platforms currently provide differing
      subsets of.
      Signed-off-by: NPaul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17178/Signed-off-by: NJames Hogan <jhogan@kernel.org>
      997e93d4
  13. 06 3月, 2018 1 次提交
    • J
      MIPS: BMIPS: Do not mask IPIs during suspend · 06a3f0c9
      Justin Chen 提交于
      Commit a3e6c1ef ("MIPS: IRQ: Fix disable_irq on CPU IRQs") fixes an
      issue where disable_irq did not actually disable the irq. The bug caused
      our IPIs to not be disabled, which actually is the correct behavior.
      
      With the addition of commit a3e6c1ef ("MIPS: IRQ: Fix disable_irq on
      CPU IRQs"), the IPIs were getting disabled going into suspend, thus
      schedule_ipi() was not being called. This caused deadlocks where
      schedulable task were not being scheduled and other cpus were waiting
      for them to do something.
      
      Add the IRQF_NO_SUSPEND flag so an irq_disable will not be called on the
      IPIs during suspend.
      Signed-off-by: NJustin Chen <justinpopo6@gmail.com>
      Fixes: a3e6c1ef ("MIPS: IRQ: Fix disabled_irq on CPU IRQs")
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/17385/
      [jhogan@kernel.org: checkpatch: wrap long lines and fix commit refs]
      Signed-off-by: NJames Hogan <jhogan@kernel.org>
      06a3f0c9
  14. 20 2月, 2018 1 次提交
  15. 19 2月, 2018 2 次提交
  16. 13 2月, 2018 2 次提交
  17. 12 2月, 2018 1 次提交
    • L
      vfs: do bulk POLL* -> EPOLL* replacement · a9a08845
      Linus Torvalds 提交于
      This is the mindless scripted replacement of kernel use of POLL*
      variables as described by Al, done by this script:
      
          for V in IN OUT PRI ERR RDNORM RDBAND WRNORM WRBAND HUP RDHUP NVAL MSG; do
              L=`git grep -l -w POLL$V | grep -v '^t' | grep -v /um/ | grep -v '^sa' | grep -v '/poll.h$'|grep -v '^D'`
              for f in $L; do sed -i "-es/^\([^\"]*\)\(\<POLL$V\>\)/\\1E\\2/" $f; done
          done
      
      with de-mangling cleanups yet to come.
      
      NOTE! On almost all architectures, the EPOLL* constants have the same
      values as the POLL* constants do.  But they keyword here is "almost".
      For various bad reasons they aren't the same, and epoll() doesn't
      actually work quite correctly in some cases due to this on Sparc et al.
      
      The next patch from Al will sort out the final differences, and we
      should be all done.
      Scripted-by: NAl Viro <viro@zeniv.linux.org.uk>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      a9a08845
  18. 08 2月, 2018 1 次提交
  19. 05 2月, 2018 2 次提交
  20. 31 1月, 2018 1 次提交