The directory drivers/reset/ is guarded by CONFIG_RESET_CONTROLLER
in driver/Makefile.

CONFIG_RESET_CONTROLLER is boolean, so it always evaluates to 'y'
in drivers/reset/Makefile.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This adds a reset controller driver to control the Xilinx Zynq
AP-SoC's various resets.
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The AR71XX/AR9XXX SoC have a simple reset controller with one bit per
reset line.
Signed-off-by: NAlban Bedel <albeu@free.fr>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Add reset driver for the Reset Generation Unit (RGU) found on NXP
LPC18xx and LPC43xx devies. This reset controller features up to 64
reset lines connected to different blocks and peripheral in the SoC.
Most reset lines on the controller are self clearing except for
those dealing with the Cortex-M0 cores on LPC43xx devices.

This driver also registers a restart handler that can be used to
reset the entire device.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Add a reset controller for Marvell Berlin SoCs which is used by the
USB PHYs drivers (for now).
Signed-off-by: NAntoine Ténart <antoine.tenart@free-electrons.com>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Add a reset-controller driver for the socfpga platform.
The reset-controller has four banks with up to 32 entries all encapsulated in
one module block.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
---

Notes:
    Changes since v2:
        - remove superfluous ret in probe function
        - add Acked-by

    Changes since v1:
        - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
        - print pdev->dev.of_node->full_name on error
        - use proper IS_ERR/PTR_ERR

This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System configuration registers are accessed through
the regmap framework and the mfd/syscon driver.

The implementation optionally supports waiting for the reset action to
be acknowledged in a separate status register and supports both
active high and active low reset lines. These properties are common across
all the reset channels in a specific reset controller instance, hence
all channels in a paritcular controller are expected to behave in the
same way.
Signed-off-by: NStephen Gallimore <stephen.gallimore@st.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>

The Allwinner A31 and most of the other Allwinner SoCs have an IP
maintaining a few other IPs in the SoC in reset by default. Among these
IPs are the A31's High Speed Timers, hence why we can't use the regular
driver construct in every cases, and need to call the registering
function directly during machine initialisation.

Apart from this, the implementation is fairly straightforward, and could
easily be moved to a generic MMIO-based reset controller driver if the
need ever arise.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>

This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NShawn Guo <shawn.guo@linaro.org>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPavel Machek <pavel@ucw.cz>