- 21 5月, 2011 5 次提交
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由 Marc Zyngier 提交于
Tested with an ARM-1136 core tile. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Acked-by: NDavid Woodhouse <dwmw2@infradead.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Marc Zyngier 提交于
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Acked-by: NDavid Woodhouse <dwmw2@infradead.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Marc Zyngier 提交于
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Acked-by: NDavid Woodhouse <dwmw2@infradead.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Marc Zyngier 提交于
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Acked-by: NDavid Woodhouse <dwmw2@infradead.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Marc Zyngier 提交于
Tested on a PB11-MPCore. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Acked-by: NDavid Woodhouse <dwmw2@infradead.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 13 5月, 2011 1 次提交
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由 Avinash H.M 提交于
The debug l3_ick/rate is not displaying the actual rate of the clock in hardware. This is because, the core dpll set_rate function doesn't update the clk.rate. After fixing, the l3_ick/rate is displaying proper values. Signed-off-by: NShweta Gulati <shweta.gulati@ti.com> Signed-off-by: NAvinash.H.M <avinashhm@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Wamsley <paul@pwsan.com> Acked-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 12 5月, 2011 4 次提交
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由 Catalin Marinas 提交于
Since mandatory barriers may be used (explicitly or implicitly via readl etc.) to ensure the ordering between Device and Normal memory accesses, a DMB is not enough. This patch converts it to a DSB. Cc: Colin Cross <ccross@android.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Arnd Bergmann 提交于
GDB's interrupt.exp test cases currenly fail on ARM. The problem is how do_signal handled restarting interrupted system calls: The entry.S assembler code determines that we come from a system call; and that information is passed as "syscall" parameter to do_signal. That routine then calls get_signal_to_deliver [*] and if a signal is to be delivered, calls into handle_signal. If a system call is to be restarted either after the signal handler returns, or if no handler is to be called in the first place, the PC is updated after the get_signal_to_deliver call, either in handle_signal (if we have a handler) or at the end of do_signal (otherwise). Now the problem is that during [*], the call to get_signal_to_deliver, a ptrace intercept may happen. During this intercept, the debugger may change registers, including the PC. This is done by GDB if it wants to execute an "inferior call", i.e. the execution of some code in the debugged program triggered by GDB. To this purpose, GDB will save all registers, allocate a stack frame, set up PC and arguments as appropriate for the call, and point the link register to a dummy breakpoint instruction. Once the process is restarted, it will execute the call and then trap back to the debugger, at which point GDB will restore all registers and continue original execution. This generally works fine. However, now consider what happens when GDB attempts to do exactly that while the process was interrupted during execution of a to-be- restarted system call: do_signal is called with the syscall flag set; it calls get_signal_to_deliver, at which point the debugger takes over and changes the PC to point to a completely different place. Now get_signal_to_deliver returns without a signal to deliver; but now do_signal decides it should be restarting a system call, and decrements the PC by 2 or 4 -- so it now points to 2 or 4 bytes before the function GDB wants to call -- which leads to a subsequent crash. To fix this problem, two things need to be supported: - do_signal must be able to recognize that get_signal_to_deliver changed the PC to a different location, and skip the restart-syscall sequence - once the debugger has restored all registers at the end of the inferior call sequence, do_signal must recognize that *now* it needs to restart the pending system call, even though it was now entered from a breakpoint instead of an actual svc instruction This set of issues is solved on other platforms, usually by one of two mechanisms: - The status information "do_signal is handling a system call that may need restarting" is itself carried in some register that can be accessed via ptrace. This is e.g. on Intel the "orig_eax" register; on Sparc the kernel defines a magic extra bit in the flags register for this purpose. This allows GDB to manage that state: reset it when doing an inferior call, and restore it after the call is finished. - On s390, do_signal transparently handles this problem without requiring GDB interaction, by performing system call restarting in the following way: first, adjust the PC as necessary for restarting the call. Then, call get_signal_to_deliver; and finally just continue execution at the PC. This way, if GDB does not change the PC, everything is as before. If GDB *does* change the PC, execution will simply continue there -- and once GDB restores the PC it saved at that point, it will automatically point to the *restarted* system call. (There is the minor twist how to handle system calls that do *not* need restarting -- do_signal will undo the PC change in this case, after get_signal_to_deliver has returned, and only if ptrace did not change the PC during that call.) Because there does not appear to be any obvious register to carry the syscall-restart information on ARM, we'd either have to introduce a new artificial ptrace register just for that purpose, or else handle the issue transparently like on s390. The patch below implements the second option; using this patch makes the interrupt.exp test cases pass on ARM, with no regression in the GDB test suite otherwise. Cc: patches@linaro.org Signed-off-by: NUlrich Weigand <ulrich.weigand@linaro.org> Signed-off-by: NArnd Bergmann <arnd.bergmann@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
The SPARSEMEM code allocates memmap entries only for sections which are present (i.e. those which contain some valid memory). The membank checks in free_unused_memmap do not take this into account and can incorrectly attempt to free memory which is not allocated, resulting in a BUG() in the bootmem code. However, if memory is configured as follows: |<----section---->|<----hole---->|<----section---->| +--------+--------+--------------+--------+--------+ | bank 0 | unused | | bank 1 | unused | +--------+--------+--------------+--------+--------+ where a bank only occupies part of a section, the memmap allocated for the remainder of the section *can* be freed. This patch modifies the checks in free_unused_memmap so that only valid memmap entries are considered for removal. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Laurent Pinchart 提交于
Commit d594f1f3 (omap: IOMMU: add support to callback during fault handling) broke interrupt line sharing between the OMAP3 ISP and its IOMMU. Because of this, every interrupt generated by the OMAP3 ISP is handled by the IOMMU driver instead of being passed to the OMAP3 ISP driver. Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: NHiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 07 5月, 2011 4 次提交
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由 Nicolas Pitre 提交于
For correctness, the initial page table located right before the decompressed kernel should be considered when determining if relocation is required. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Tested-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com>
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由 Nicolas Pitre 提交于
If the zImage load address is slightly below the relocation address, there is a risk for the copied data to overwrite the copy loop or cache flush code that the relocation process requires. Always bump the relocation address by the size of that code to avoid this issue. Noticed by Tony Lindgren <tony@atomide.com>. While at it, let's start the copy from the restart symbol which makes the above code size computation possible by the assembler directly (same sections), given that we don't need to preserve the code before that point anyway. And therefore we don't need to carry the _start pointer in r5 anymore. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Tested-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Otherwise cache_clean_flush can overwrite some of the relocated area depending on where the kernel image gets loaded. This fixes booting on n900 after commit 6d7d0ae5 (ARM: 6750/1: improvements to compressed/head.S). Thanks to Aaro Koskinen <aaro.koskinen@nokia.com> for debugging the address of the relocated area that gets corrupted, and to Nicolas Pitre <nicolas.pitre@linaro.org> for the other uncompress related fixes. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Nicolas Pitre 提交于
With ARMv5+ and EABI, the compiler expects a 64-bit aligned stack so instructions like STRD and LDRD can be used. Without this, mysterious boot failures were seen semi randomly with the LZMA decompressor. While at it, let's align .bss as well. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Tested-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com> CC: stable@kernel.org
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- 29 4月, 2011 26 次提交
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由 Dan Rosenberg 提交于
When CONFIG_OABI_COMPAT is set, the wrapper for semtimedop does not bound the nsops argument. A sufficiently large value will cause an integer overflow in allocation size, followed by copying too much data into the allocated buffer. Fix this by restricting nsops to SEMOPM. Untested. Cc: stable@kernel.org Signed-off-by: NDan Rosenberg <drosenberg@vsecurity.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jon Medhurst 提交于
- Remove coding standard violations reported by checkpatch.pl - Delete comment about handling of conditional branches which is no longer true. - Delete comment at end of file which lists all ARM instructions. This duplicates data available in the ARM ARM and seems like an unnecessary maintenance burden to keep this up to date and accurate. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
Being able to probe NOP instructions is useful for hard-coding probeable locations and is used by the kprobes test code. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
These bit field manipulation instructions occur several thousand times in an ARMv7 kernel. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The MOVW and MOVT instructions account for approximately 7% of all instructions in a ARMv7 kernel as GCC uses them instead of a literal pool. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The instruction decoding in space_cccc_000x needs to reject probing of instructions with undefined patterns as they may in future become defined and then emulated faultily - as has already happened with the SMC instruction. This fix is achieved by testing for the instruction patterns we want to probe and making the the default fall-through paths reject probes. This also allows us to remove some explicit tests for instructions that we wish to reject, as that is now the default action. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The tests to explicitly reject probing CPS, RFE and SRS instructions are redundant as the default case is now to reject undecoded patterns. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The PLD instructions wasn't being decoded correctly and the emulation code wasn't adjusting PC correctly. As the PLD instruction is only a performance hint we emulate it as a simple nop, and we can broaden the instruction decoding to take into account newer PLI and PLDW instructions. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The emulation of SETEND was broken as it changed the endianess for the running kprobes handling code. Rather than adding a new simulation routine to fix this we'll just reject probing of SETEND as these should be very rare in the kernel. Note, the function emulate_none is now unused but it is left in the source code as future patches will use it. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
Following the change to remove support for coprocessor instructions we are left with three stub functions which can be consolidated. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The kernel doesn't currently support VFP or Neon code, and probing of code with CP15 operations is fraught with bad consequences. Therefore we don't need the ability to probe coprocessor instructions and the code to support this can be removed. The removed code also had at least two bugs: - MRC into R15 should set CPSR not trash PC - LDC and STC which use PC as base register needed the address offset by 8 Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The USAD8 instruction wasn't being explicitly decoded leading to the incorrect emulation routine being called. It can be correctly decoded in the same way as the signed multiply instructions so we move the decoding there. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The signed multiply instructions were being decoded incorrectly. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
These sign extension instructions are encoded as extend-and-add instructions where the register to add is specified as r15. The decoding routines weren't checking for this and were using the incorrect emulation code, giving incorrect results. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The instructions space for media instructions contains some undefined patterns. We need to reject probing of these because they may in future become defined and the kprobes code may then emulate them faultily. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The v6T2 RBIT instruction was accidentally being emulated correctly, this patch adds correct decoding for the instruction. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
These instructions are specified as UNPREDICTABLE. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The decoding of these instructions got the register indexed and immediate indexed forms the wrong way around, causing incorrect emulation. Instructions like "LDRD Rx, [Rx]" were corrupting Rx because the base register writeback was being performed unconditionally, overwriting the value just loaded from memory. The fix is to only writeback the base register when that form of the instruction is used. Note, now that we reject probing writeback with PC the emulation code doesn't need the check rn!=15. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
Using PC as an base register with writeback is UNPREDICTABLE, as is non word-sized loads or stores of PC. (We only really care about preventing loads to PC but it keeps the code simpler if we also exclude stores.) Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The decoding of these instructions got the register indexed and immediate indexed forms the wrong way around, causing incorrect emulation. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The emulation code for STREX and LDREX instructions is faulty, however, rather than attempting to fix this we reject probes of these instructions. We do this because they can never succeed in gaining exclusive access as the exception framework clears the exclusivity monitor when a probes breakpoint is hit. (This is a general problem when probing all instructions executing between a LDREX and its corresponding STREX and can lead to infinite retry loops.) Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The instructions space for 'Multiply and multiply-accumulate' instructions contains some undefined patterns. We need to reject probing of these because they may in future become defined and the kprobes code may then emulate them faultily. This has already happened with the new MLS instruction which this patch also adds correct decoding for as well as tightening up other decoding tests. (Before this patch the wrong emulation routine was being called for MLS though it still produced correct results.) Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
The MRS instruction should set mode and interrupt bits in the read value so it is simpler to use a new simulation routine (simulate_mrs) rather than some modified emulation. prep_emulate_rd12 is now unused and removed. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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由 Jon Medhurst 提交于
We need to reject probing of instructions which read SPSR because we can't handle this as the value in SPSR is lost when the exception handler for the probe breakpoint first runs. This patch also fixes the bitmask for MRS instructions decoding to include checking bits 5-7. Signed-off-by: NJon Medhurst <tixy@yxit.co.uk> Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
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