- 04 9月, 2014 1 次提交
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由 Linus Walleij 提交于
commit 2243a87d "pinctrl: avoid duplicated calling enable_pinmux_setting for a pin" removed the .disable callback from the struct pinmux_ops, making the .enable() callback the only remaining callback. However .enable() is a bad name as it seems to imply that a muxing can also be disabled. Rename the callback to .set_mux() and also take this opportunity to clean out any remaining mentions of .disable() from the documentation. Acked-by: NStephen Warren <swarren@nvidia.com> Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: NFan Wu <fwu@marvell.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 29 8月, 2014 2 次提交
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由 Keerthy 提交于
AM437x pinctrl definitions now differ from traditional 16 bit OMAP pin ctrl definitions, in that all 32 bits are used to describe a single pin Also the location of wakeupenable and event bits have changed. Signed-off-by: NKeerthy <j-keerthy@ti.com> [nm@ti.com: minor updates] Signed-off-by: NNishanth Menon <nm@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Nishanth Menon 提交于
DRA7 pinctrl definitions now differ from traditional 16 bit OMAP pin ctrl definitions, in that all 32 bits are used to describe a single pin Also the location of wakeupenable and event bits have changed. Signed-off-by: NNishanth Menon <nm@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 11 7月, 2014 3 次提交
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由 Rickard Strandqvist 提交于
%d in format string used, but the type is unsigned int This was found using a static code analysis program called cppcheck Signed-off-by: NRickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Rickard Strandqvist 提交于
Remove variable that are never used This was found using a static code analysis program called cppcheck. Signed-off-by: NRickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Fan Wu 提交于
What the patch does: 1. Call pinmux_disable_setting ahead of pinmux_enable_setting each time pinctrl_select_state is called 2. Remove the HW disable operation in pinmux_disable_setting function. 3. Remove the disable ops in struct pinmux_ops 4. Remove all the disable ops users in current code base. Notes: 1. Great thanks for the suggestion from Linus, Tony Lindgren and Stephen Warren and Everyone that shared comments on this patch. 2. The patch also includes comment fixes from Stephen Warren. The reason why we do this: 1. To avoid duplicated calling of the enable_setting operation without disabling operation inbetween which will let the pin descriptor desc->mux_usecount increase monotonously. 2. The HW pin disable operation is not useful for any of the existing platforms. And this can be used to avoid the HW glitch after using the item #1 modification. In the following case, the issue can be reproduced: 1. There is a driver that need to switch pin state dynamically, e.g. between "sleep" and "default" state 2. The pin setting configuration in a DTS node may be like this: component a { pinctrl-names = "default", "sleep"; pinctrl-0 = <&a_grp_setting &c_grp_setting>; pinctrl-1 = <&b_grp_setting &c_grp_setting>; } The "c_grp_setting" config node is totally identical, maybe like following one: c_grp_setting: c_grp_setting { pinctrl-single,pins = <GPIO48 AF6>; } 3. When switching the pin state in the following official pinctrl sequence: pin = pinctrl_get(); state = pinctrl_lookup_state(wanted_state); pinctrl_select_state(state); pinctrl_put(); Test Result: 1. The switch is completed as expected, that is: the device's pin configuration is changed according to the description in the "wanted_state" group setting 2. The "desc->mux_usecount" of the corresponding pins in "c_group" is increased without being decreased, because the "desc" is for each physical pin while the setting is for each setting node in the DTS. Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount will keep increasing without any chance to be decreased. According to the comments in the original code, only the setting, in old state but not in new state, will be "disabled" (calling pinmux_disable_setting), which is correct logic but not intact. We still need consider case that the setting is in both old state and new state. We can do this in the following two ways: 1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin setting" repeatedly 2. "Disable"(calling pinmux_disable_setting) the "same pin setting", actually two setting instances, ahead of enabling them. Analysis: 1. The solution #2 is better because it can avoid too much iteration. 2. If we disable all of the settings in the old state and one of the setting(s) exist in the new state, the pins mux function change may happen when some SoC vendors defined the "pinctrl-single,function-off" in their DTS file. old_setting => disabled_setting => new_setting. 3. In the pinmux framework, when a pin state is switched, the setting in the old state should be marked as "disabled". Conclusion: 1. To Remove the HW disabling operation to above the glitch mentioned above. 2. Handle the issue mentioned above by disabling all of the settings in old state and then enable the all of the settings in new state. Signed-off-by: NFan Wu <fwu@marvell.com> Acked-by: NStephen Warren <swarren@nvidia.com> Acked-by: NPatrice Chotard <patrice.chotard@st.com> Acked-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 23 4月, 2014 1 次提交
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由 Tony Lindgren 提交于
Since we set up device wake-up interrupts as pinctrl-single interrupts, we now must use the standard request_irq and related functions to manage them. If the pin interrupts are enabled for some pins at boot, the wake-up events can show up as constantly pending at least on omaps and will hang the system unless the related device driver clears the event at the device. To fix this, let's clear the interrupt flags during init, and print out a warning so the board maintainers can update their drivers to do proper request_irq for the driver specific wake-up events. Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 2月, 2014 1 次提交
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由 Chao Xie 提交于
For some silicons, the pin configuration register can control the output of the pin when the pad including the pin enter low power mode. For example, the pin can be "Drive 1", "Drive 0", "Float" when the pad including the pin enter low power mode. It is very useful when you want to control the power leakeage when the SOC enter low power mode, and can save more power for the low power mode. Signed-off-by: NChao Xie <chao.xie@marvell.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 1月, 2014 2 次提交
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由 Tomi Valkeinen 提交于
commit 4e7e8017 (pinctrl: pinctrl-single: enhance to configure multiple pins of different modules) improved support for pinctrl-single,bits option, but also caused a regression in parsing badly configured mask data. If the masks in DT data are not quite right, pcs_parse_bits_in_pinctrl_entry() can end up in an infinite loop, trashing memory at the same time. Add a check to verify that each loop actually removes bits from the 'mask', so that the loop can eventually end. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tomi Valkeinen 提交于
pcs_enable() uses vals->mask instead of pcs->fmask when bits_per_mux is enabled. However, pcs_disable() always uses pcs->fmask. Fix pcs_disable() to use vals->mask with bits_per_mux. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 11月, 2013 1 次提交
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由 Roger Quadros 提交于
On OMAPs the IO ring must be rearmed each time the pad wakeup configuration is changed. So call pcs_soc->rearm() from pcs_irq_set(). As pinctrl-single is now an interrupt controller in some cases, we should follow the standards and keep the interrupts enabled constantly, and not just for wake-up events. The tracking of runtime vs wake-up interrupts can be handled separately for the automated runtime PM solution when we have it in the future. Signed-off-by: NRoger Quadros <rogerq@ti.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> [tony@atomide.com: removed wrong comment, updated description] Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 19 10月, 2013 1 次提交
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由 Tony Lindgren 提交于
Looks like we need a little bit of arch specific handling with the generic IRQ. Fix the issue with an ifdef the same way as other drivers do. ARM needs things set to IRQF_VALID, which also then sets noprobe. Others seem to use just irq_set_noprobe(). Otherwise we can get: drivers/pinctrl/pinctrl-single.c: In function 'pcs_irqdomain_map': drivers/pinctrl/pinctrl-single.c:1750:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration] drivers/pinctrl/pinctrl-single.c:1750:21: error: 'IRQF_VALID' undeclared (first use in this function) drivers/pinctrl/pinctrl-single.c:1750:34: error: 'IRQF_PROBE' undeclared (first use in this function) Reported-by: NRandy Dunlap <rdunlap@infradead.org> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 11 10月, 2013 2 次提交
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由 Tony Lindgren 提交于
For omaps, we still have dependencies to the legacy code for handling the PRM (Power Reset Management) interrupts, and also for reconfiguring the io wake-up chain after changes. Let's pass the PRM interrupt and the rearm functions via auxdata. Then when at some point we have a proper PRM driver, we can get the interrupt via device tree and set up the rearm function as exported function in the PRM driver. By using auxdata we can remove a dependency to the wake-up events for converting omap3 to be device tree only. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Prakash Manjunathappa <prakash.pm@ti.com> Cc: Roger Quadros <rogerq@ti.com> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: linux-kernel@vger.kernel.org Reviewed-by: NKevin Hilman <khilman@linaro.org> Tested-by: NKevin Hilman <khilman@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
The pin control registers can have interrupts for example for device wake-up. These interrupts can be treated as a chained interrupt controller as suggested earlier by Linus Walleij <linus.walleij@linaro.org>. This patch adds support for interrupts in a way that should be pretty generic, and works for the omaps that support wake-up interrupts. On omaps, there's an interrupt enable and interrupt status bit for each pin. The two pinctrl domains on omaps share a single interrupt from the PRM chained interrupt handler. Support for other similar hardware should be easy to add. Note that this patch does not attempt to handle the wake-up interrupts automatically unlike the earlier patches. This patch allows the device drivers to do a request_irq() on the wake-up pins as needed. I'll try to do also a separate generic patch for handling the wake-up events automatically. Also note that as this patch makes the pinctrl-single an irq controller, the current bindings need some extra trickery to use interrupts from two different interrupt controllers for the same driver. So it might be worth waiting a little on the patches enabling the wake-up interrupts from drivers as there should be a generic way to handle it coming. And also there's been discussion of interrupts-extended binding for using interrupts from multiple interrupt controllers. In any case, this patch should be ready to go allowing handling the wake-up interrupts in a generic way, or separately from the device drivers. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Prakash Manjunathappa <prakash.pm@ti.com> Cc: Roger Quadros <rogerq@ti.com> Cc: linux-kernel@vger.kernel.org Cc: Benoît Cousson <bcousson@baylibre.com> Cc: devicetree@vger.kernel.org Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: NKevin Hilman <khilman@linaro.org> Tested-by: NKevin Hilman <khilman@linaro.org> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 10 10月, 2013 1 次提交
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由 Tony Lindgren 提交于
Let's replace is_pinconf with flags and add struct pcs_soc_data so we can support SoC specific features like pin wake-up events. Done in collaboration with Roger Quadros <rogerq@ti.com>. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Prakash Manjunathappa <prakash.pm@ti.com> Cc: linux-kernel@vger.kernel.org Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: NKevin Hilman <khilman@linaro.org> Tested-by: NKevin Hilman <khilman@linaro.org> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 28 8月, 2013 1 次提交
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由 Sherman Yin 提交于
When setting pin configuration in the pinctrl framework, pin_config_set() or pin_config_group_set() is called in a loop to set one configuration at a time for the specified pin or group. This patch 1) removes the loop and 2) changes the API to pass the whole pin config array to the driver. It is now up to the driver to loop through the configs. This allows the driver to potentially combine configs and reduce the number of writes to pin config registers. All c files changed have been build-tested to verify the change compiles and that the corresponding .o is successfully generated. Signed-off-by: NSherman Yin <syin@broadcom.com> Reviewed-by: NChristian Daudt <csd@broadcom.com> Reviewed-by: NMatt Porter <matt.porter@linaro.org> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 23 7月, 2013 1 次提交
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由 Jean-Francois Moine 提交于
This warning has been introduced by the commit 0f9bc4bc pinctrl: single: adopt pinctrl sleep mode management Signed-off-by: NJean-Francois Moine <moinejf@free.fr> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 18 6月, 2013 1 次提交
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由 Hebbar Gururaja 提交于
Make pinctrl-single able to handle suspend/resume events and change hogged pins states accordingly. Signed-off-by: NHebbar Gururaja <gururaja.hebbar@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 16 6月, 2013 2 次提交
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由 Manjunathappa, Prakash 提交于
Take care to name pin names as register-offset.bit-pos-of-pin-in-register in case configuring multiple pins in register. Signed-off-by: NManjunathappa, Prakash <prakash.pm@ti.com> Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Manjunathappa, Prakash 提交于
Add support to configure multiple pins in each register, existing implementation added by [1] does not support full fledge multiple pin configuration in single register, reports a pin clash when different modules configure different bits of same register. The issue reported and discussed here http://www.spinics.net/lists/arm-kernel/msg235213.html With pinctrl-single,bits-per-mux property specified, use function-mask property to find out number pins to configure. Allocate and register pin control functions based sub mask. Tested on da850/omap-l138 EVM. does not support variable submask for pins. does not support pinconf. [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" (9e605cb6), Signed-off-by: NManjunathappa, Prakash <prakash.pm@ti.com> Reported-by: NLad, Prabhakar <prabhakar.csengg@gmail.com> Tested-by: NLad, Prabhakar <prabhakar.csengg@gmail.com> Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 14 5月, 2013 1 次提交
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由 Wei Yongjun 提交于
Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Introduced by commit 9dddb4df (pinctrl: single: support generic pinconf) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 14 3月, 2013 1 次提交
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由 Haojian Zhuang 提交于
pcs_pinconf_set() is always using "arg << shift" to configure two parameters case. But pcs_add_conf2() didn't remove shift for config argument. So correct it. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 07 3月, 2013 5 次提交
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由 Axel Lin 提交于
If pcs->is_pinconf is false, it means does not support pinconf. If pcs->is_pinconf is true, is_generic flag is always true. This patch fixes below build error: CC [M] drivers/pinctrl/pinctrl-single.o drivers/pinctrl/pinctrl-single.c: In function 'pcs_probe': drivers/pinctrl/pinctrl-single.c:1441:3: error: assignment of member 'is_generic' in read-only object make[2]: *** [drivers/pinctrl/pinctrl-single.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 Signed-off-by: NAxel Lin <axel.lin@ingics.com> Reviewed-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Haojian Zhuang 提交于
Support the operation of generic pinconf. The supported config arguments are INPUT_SCHMITT, INPUT_SCHMITT_ENABLE, DRIVE_STRENGHT, BIAS_DISABLE, BIAS_PULLUP, BIAS_PULLDOWN, SLEW_RATE. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Haojian Zhuang 提交于
Since Hisilicon's pin controller is divided into two parts. One is the function mux, and the other is pin configuration. These two parts are in the different memory regions. So make pinctrl-single,function-mask as optional property. Then we can define pingroups without valid function mux that is only used for pin configuration. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Haojian Zhuang 提交于
Since gpio driver could create gpio range in DTS, it could invoke pinctrl_request_gpio(). In the pinctrl-single driver, it needs to configure pins with gpio function mode. A new gpio function range should be created in DTS file in below. pinctrl-single,gpio-range = <phandle pin_offset nr_pins gpio_func>; range: gpio-range { #pinctrl-single,gpio-range-cells = <3>; }; The gpio-ranges property is used in gpio driver and the pinctrl-single,gpio-range property is used in pinctrl-single driver. 1. gpio-ranges is used for gpio driver in below. gpio-ranges = <phandle gpio_offset_in_chip pin_offset nr_pins> gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; 2. gpio driver could get pin offset from gpio-ranges property. pinctrl-single driver could get gpio function mode from gpio_func that is stored in @gpiofuncs list in struct pcs_device. This new pinctrl-single,gpio-range is used as complement for gpio-ranges property in gpio driver. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Laurent Pinchart 提交于
The pinconf, pinctrl and pinmux operation structures hold function pointers that are never modified. Declare them as const. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 1月, 2013 1 次提交
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由 Haojian Zhuang 提交于
This reverts commit 2e8b2eab. Conflicts: drivers/pinctrl/pinctrl-single.c ERROR: "__aeabi_uldivmod" [drivers/pinctrl/pinctrl-single.ko] undefined!] On Fri, Jan 11, 2013 at 4:00 PM, Russell King wrote: > The above error happens in builds including pinctrl-single - the > reason > is this, where resource_size_t may be 64-bit. > > gpio->range.pin_base = (r.start - pcs->res->start) / > mux_bytes; > gpio->range.npins = (r.end - r.start) / mux_bytes + 1; The reason of not fixing this issue and reverting the patch instead is this patch can't handle another case. It's not easy to handle multiple gpios sharing one pin register. So this gpio range feature will be implemented by other patches. Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 04 1月, 2013 1 次提交
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由 Greg Kroah-Hartman 提交于
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Barry Song <baohua.song@csr.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 29 11月, 2012 3 次提交
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由 Bill Pemberton 提交于
CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: NBill Pemberton <wfp5p@virginia.edu> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Bill Pemberton 提交于
CONFIG_HOTPLUG is going away as an option so __devinitdata is no longer needed. Signed-off-by: NBill Pemberton <wfp5p@virginia.edu> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Bill Pemberton 提交于
CONFIG_HOTPLUG is going away as an option so __devexit_p is no longer needed. Signed-off-by: NBill Pemberton <wfp5p@virginia.edu> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 23 11月, 2012 1 次提交
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由 Sachin Kamat 提交于
*map should be tested for NULL instead of map. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 11月, 2012 1 次提交
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由 Haojian Zhuang 提交于
Marvell's PXA/MMP silicon also match the behavior of pinctrl-single. Each pin binds to one register. A lot of pins could be configured as gpio. GPIO range is defined as a child node of pinmux in .dtsi file. If those pins are with the same gpio function configuration in the pinmux register, they could be defined in the same GPIO range. For this new child node, two properties are used. reg = <the start of pinmux register in range, size of range> pinctrl-single,gpio: <gpio base in range, the gpio function of the range in the pinmux register> Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 11月, 2012 1 次提交
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由 Haojian Zhuang 提交于
Dump pinmux register value, not only function part in the pinmux register. Also fix the issue on caluclating pin offset. The last parameter should be pin number, not register offset. Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 28 9月, 2012 1 次提交
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由 Matt Porter 提交于
Adds support for displaying the individual pin h/w config state. Signed-off-by: NMatt Porter <mporter@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 13 9月, 2012 1 次提交
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由 Peter Ujfalusi 提交于
With pinctrl-single,bits it is possible to update just part of the register within the pinctrl-single,function-mask area. This is useful when one register configures mmore than one pin's mux. pinctrl-single,bits takes three parameters: <reg offset, value, sub-mask> Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> [Removed a misplaced comment] Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 9月, 2012 1 次提交
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由 Peter Ujfalusi 提交于
Use the pcs->fmask to make sure that the value is not changing (setting) bits in areas where it should not. To avoid situations like this: pmx_dummy: pinmux@4a100040 { compatible = "pinctrl-single"; reg = <0x4a100040 0x0196>; #address-cells = <1>; #size-cells = <0>; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x00ff>; }; &pmx_dummy { pinctrl-names = "default"; pinctrl-0 = <&board_pins>; board_pins: pinmux_board_pins { pinctrl-single,pins = < 0x6c 0xf0f 0x6e 0x10f 0x70 0x23f 0x72 0xa5f >; }; }; Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 7月, 2012 1 次提交
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由 Tony Lindgren 提交于
Add one-register-per-pin type device tree based pinctrl driver. This driver has been tested on omap2+ series of processors, where there is either an 8 or 16-bit padconf register for each pin. Support for other similar pinmux controllers can be added. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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