The hardware just doesn't support this correctly.
Disable it before we accidentally write anywhere we shouldn't.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Give the ring functions a separate structure and let the asic
structure point to the ring specific functions. This simplifies
the code and allows us to make changes at only one point.

No change in functionality.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Starting on CIK, multi-media blocks like UVD no longer
have special power state.  Rather they have their own
DPM implementation which adjusts their clocks dynamically
when active.  When they are not active, the blocks are
powergated to save power.

v2: add missing pm locks
v3: rebase on uvd state selection rework
v4: fix inverted logic typo noticed by Christian
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching

Set radeon.dpm=1 to enable.

v2: remove unused radeon_atombios.c changes,
    make missing smc ucode non-fatal
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Used for vce power management.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for dpm on CI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Needed for DPM on CI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Uses a different table format if the board supports EVV.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

No support for reading temperature back yet.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Used for uvd power management.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

and remove duplicate si_rlc functions.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

1. Handle the the thermal state directly in the work handler.
Remove the state selection function since nothing else uses it now.
2. On some asics there is no thermal state, so we just use a regular
state and force the low performance state.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use the UVD handle information to determine which
which power states to select when using UVD.  For
example, decoding a single SD stream requires much
lower clocks than multiple HD streams.

v2: switch to a cleaner dpm/uvd interface
v3: change the uvd power state while streams
are active if need be
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add a helper function for counting the number of open stream handles.

v2: fix copy-pasta in comments and whitespace error
v3: make function static since it's only used in radeon_uvd.c
at the moment
v4: make non-static again for future changes
v5: make static again for new rework of dpm uvd changes
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

No longer used now that we use the async dma engines or
CP DMA for bo copies.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This bug (introduced in 3.10) in WREG32_OR made
commit d3418eac
"drm/radeon/evergreen: setup HDMI before enabling it"
cause a regression. Sometimes audio over HDMI wasn't working, sometimes
display was corrupted.

This fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=60687
https://bugzilla.kernel.org/show_bug.cgi?id=60709
https://bugs.freedesktop.org/show_bug.cgi?id=67767Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We need proper locking in the driver when accessing instanced
registers on CIK.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Otherwise just reinitialize from scratch on resume,
and so make it more likely to succeed.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Can cause hangs when enabled in certain motherboards.
Set radeon.aspm=0 to disable aspm.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Covers requirements of all current asics.
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

There are cases where we need more than 4k alignment.  No
functional change with this commit.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Changing the UVD BOs offset on suspend/resume doesn't work because the VCPU
internally keeps pointers to it. Just keep it always pinned and save the
content manually.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66425

v2: fix compiler warning
v3: fix CIK support

Note: a version of this patch needs to go to stable.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If the vblank time is too short to adjust mclk,
assume multiple displays (no mclk adjustments).
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This allows you to force specific power levels within a power
state.  Due to hardware restrictions between generations, the
interface is limited to the following 3 selections:

auto: all levels enabled
low: forced to the lowest power level
high: forced to the highest power level
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Certain older rv770 asics have both a performance and
a 3D performance state rather than just multiple performance
levels in the state power state.  The current code would
select the performance state rather than the 3D performance
state when the "performance" profile was selected.  This change
switches to the "balanced" profile by default which ends up being
the internal performance profile.  When the user selects the
"performance" profile, it selects the internal 3D performance
state so the user can select the higher performance modes.

For most asics this changes nothing.  For certain rv770 asics
with static performance and 3D performance states, this allows
you to select between then using by selecting the "balanced"
and "performance" dpm profiles.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This lays the frameworks to report realtime power level
feedback.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This commit converts the source of the val_seq counter to
the ww_mutex api. The reservation objects are converted later,
because there is still a lockdep splat in nouveau that has to
resolved first.
Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@canonical.com>
Reviewed-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

This adds dpm support for SI asics.  This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2/gen3 switching
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.

v2: enable hainan support, rebase
v3: guard acpi stuff
v4: fix 64 bit math
v5: fix 64 bit div harder
v6: fix thermal interrupt check noticed by Jerome
v7: attempt fix state enable
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Validate the voltages against the voltage requirements of the
dispclk.  We currently don't adjust the disp clock so it never
changes, but we need to filter out voltage levels that are too
low none the less.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Used by SI dpm.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for dpm on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This makes it easier the understand what the code is
doing.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These are needed for certain UVD power saving features.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Required for accessing certain pcie related registers.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SI uses a new atom table revision.  Required for DPM on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>