1. 07 6月, 2017 10 次提交
  2. 06 6月, 2017 1 次提交
  3. 02 6月, 2017 1 次提交
  4. 27 5月, 2017 1 次提交
  5. 18 5月, 2017 3 次提交
  6. 10 5月, 2017 3 次提交
    • N
      uapi: export all headers under uapi directories · fcc8487d
      Nicolas Dichtel 提交于
      Regularly, when a new header is created in include/uapi/, the developer
      forgets to add it in the corresponding Kbuild file. This error is usually
      detected after the release is out.
      
      In fact, all headers under uapi directories should be exported, thus it's
      useless to have an exhaustive list.
      
      After this patch, the following files, which were not exported, are now
      exported (with make headers_install_all):
      asm-arc/kvm_para.h
      asm-arc/ucontext.h
      asm-blackfin/shmparam.h
      asm-blackfin/ucontext.h
      asm-c6x/shmparam.h
      asm-c6x/ucontext.h
      asm-cris/kvm_para.h
      asm-h8300/shmparam.h
      asm-h8300/ucontext.h
      asm-hexagon/shmparam.h
      asm-m32r/kvm_para.h
      asm-m68k/kvm_para.h
      asm-m68k/shmparam.h
      asm-metag/kvm_para.h
      asm-metag/shmparam.h
      asm-metag/ucontext.h
      asm-mips/hwcap.h
      asm-mips/reg.h
      asm-mips/ucontext.h
      asm-nios2/kvm_para.h
      asm-nios2/ucontext.h
      asm-openrisc/shmparam.h
      asm-parisc/kvm_para.h
      asm-powerpc/perf_regs.h
      asm-sh/kvm_para.h
      asm-sh/ucontext.h
      asm-tile/shmparam.h
      asm-unicore32/shmparam.h
      asm-unicore32/ucontext.h
      asm-x86/hwcap2.h
      asm-xtensa/kvm_para.h
      drm/armada_drm.h
      drm/etnaviv_drm.h
      drm/vgem_drm.h
      linux/aspeed-lpc-ctrl.h
      linux/auto_dev-ioctl.h
      linux/bcache.h
      linux/btrfs_tree.h
      linux/can/vxcan.h
      linux/cifs/cifs_mount.h
      linux/coresight-stm.h
      linux/cryptouser.h
      linux/fsmap.h
      linux/genwqe/genwqe_card.h
      linux/hash_info.h
      linux/kcm.h
      linux/kcov.h
      linux/kfd_ioctl.h
      linux/lightnvm.h
      linux/module.h
      linux/nbd-netlink.h
      linux/nilfs2_api.h
      linux/nilfs2_ondisk.h
      linux/nsfs.h
      linux/pr.h
      linux/qrtr.h
      linux/rpmsg.h
      linux/sched/types.h
      linux/sed-opal.h
      linux/smc.h
      linux/smc_diag.h
      linux/stm.h
      linux/switchtec_ioctl.h
      linux/vfio_ccw.h
      linux/wil6210_uapi.h
      rdma/bnxt_re-abi.h
      
      Note that I have removed from this list the files which are generated in every
      exported directories (like .install or .install.cmd).
      
      Thanks to Julien Floret <julien.floret@6wind.com> for the tip to get all
      subdirs with a pure makefile command.
      
      For the record, note that exported files for asm directories are a mix of
      files listed by:
       - include/uapi/asm-generic/Kbuild.asm;
       - arch/<arch>/include/uapi/asm/Kbuild;
       - arch/<arch>/include/asm/Kbuild.
      Signed-off-by: NNicolas Dichtel <nicolas.dichtel@6wind.com>
      Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Acked-by: NRussell King <rmk+kernel@armlinux.org.uk>
      Acked-by: NMark Salter <msalter@redhat.com>
      Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
      Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      fcc8487d
    • D
      sparc64: fix fault handling in NGbzero.S and GENbzero.S · 3c7f6221
      Dave Aldridge 提交于
      When any of the functions contained in NGbzero.S and GENbzero.S
      vector through *bzero_from_clear_user, we may end up taking a
      fault when executing one of the store alternate address space
      instructions. If this happens, the exception handler does not
      restore the %asi register.
      
      This commit fixes the issue by introducing a new exception
      handler that ensures the %asi register is restored when
      a fault is handled.
      
      Orabug: 25577560
      Signed-off-by: NDave Aldridge <david.j.aldridge@oracle.com>
      Reviewed-by: NRob Gardner <rob.gardner@oracle.com>
      Reviewed-by: NBabu Moger <babu.moger@oracle.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3c7f6221
    • G
      sparc: use memdup_user_nul in sun4m LED driver · aed74ea0
      Geliang Tang 提交于
      Use memdup_user_nul() helper instead of open-coding to simplify the code.
      Signed-off-by: NGeliang Tang <geliangtang@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      aed74ea0
  7. 03 5月, 2017 1 次提交
  8. 02 5月, 2017 1 次提交
    • D
      sparc64: Fix BPF JIT wrt. branches and ldimm64 instructions. · e3bf4c61
      David S. Miller 提交于
      Like other JITs, sparc64 maintains an array of instruction offsets but
      stores the entries off by one.  This is done because jumps to the
      exit block are indexed to one past the last BPF instruction.
      
      So if we size the array by the program length, we need to record
      the previous instruction in order to stay within the array bounds.
      
      This is explained in ARM JIT commit 8eee539d ("arm64: bpf: fix
      out-of-bounds read in bpf2a64_offset()").
      
      But this scheme requires a little bit of careful handling when
      the instruction before the branch destination is a 64-bit load
      immediate.  It takes up 2 BPF instruction slots.
      
      Therefore, we have to fill in the array entry for the second
      half of the 64-bit load immediate instruction rather than for
      the one for the beginning of that instruction.
      
      Fixes: 7a12b503 ("sparc64: Add eBPF JIT.")
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e3bf4c61
  9. 27 4月, 2017 2 次提交
  10. 25 4月, 2017 2 次提交
    • D
      sparc64: Improve 64-bit constant loading in eBPF JIT. · 14933dc8
      David S. Miller 提交于
      Doing a full 64-bit decomposition is really stupid especially for
      simple values like 0 and -1.
      
      But if we are going to optimize this, go all the way and try for all 2
      and 3 instruction sequences not requiring a temporary register as
      well.
      
      First we do the easy cases where it's a zero or sign extended 32-bit
      number (sethi+or, sethi+xor, respectively).
      
      Then we try to find a range of set bits we can load simply then shift
      up into place, in various ways.
      
      Then we try negating the constant and see if we can do a simple
      sequence using that with a xor at the end.  (f.e. the range of set
      bits can't be loaded simply, but for the negated value it can)
      
      The final optimized strategy involves 4 instructions sequences not
      needing a temporary register.
      
      Otherwise we sadly fully decompose using a temp..
      
      Example, from ALU64_XOR_K: 0x0000ffffffff0000 ^ 0x0 = 0x0000ffffffff0000:
      
      0000000000000000 <foo>:
         0:   9d e3 bf 50     save  %sp, -176, %sp
         4:   01 00 00 00     nop
         8:   90 10 00 18     mov  %i0, %o0
         c:   13 3f ff ff     sethi  %hi(0xfffffc00), %o1
        10:   92 12 63 ff     or  %o1, 0x3ff, %o1     ! ffffffff <foo+0xffffffff>
        14:   93 2a 70 10     sllx  %o1, 0x10, %o1
        18:   15 3f ff ff     sethi  %hi(0xfffffc00), %o2
        1c:   94 12 a3 ff     or  %o2, 0x3ff, %o2     ! ffffffff <foo+0xffffffff>
        20:   95 2a b0 10     sllx  %o2, 0x10, %o2
        24:   92 1a 60 00     xor  %o1, 0, %o1
        28:   12 e2 40 8a     cxbe  %o1, %o2, 38 <foo+0x38>
        2c:   9a 10 20 02     mov  2, %o5
        30:   10 60 00 03     b,pn   %xcc, 3c <foo+0x3c>
        34:   01 00 00 00     nop
        38:   9a 10 20 01     mov  1, %o5     ! 1 <foo+0x1>
        3c:   81 c7 e0 08     ret
        40:   91 eb 40 00     restore  %o5, %g0, %o0
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      14933dc8
    • D
      sparc64: Support cbcond instructions in eBPF JIT. · e3a724ed
      David S. Miller 提交于
      cbcond combines a compare with a branch into a single instruction.
      
      The limitations are:
      
      1) Only newer chips support it
      
      2) For immediate compares we are limited to 5-bit signed immediate
         values
      
      3) The branch displacement is limited to 10-bit signed
      
      4) We cannot use it for JSET
      
      Also, cbcond (unlike all other sparc control transfers) lacks a delay
      slot.
      
      Currently we don't have a useful instruction we can push into the
      delay slot of normal branches.  So using cbcond pretty much always
      increases code density, and is therefore a win.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e3a724ed
  11. 24 4月, 2017 2 次提交
  12. 23 4月, 2017 2 次提交
  13. 20 4月, 2017 1 次提交
  14. 19 4月, 2017 4 次提交
  15. 15 4月, 2017 2 次提交
    • T
      sparc/sysfs: Replace racy task affinity logic · ea875ec9
      Thomas Gleixner 提交于
      The mmustat_enable sysfs file accessor functions must run code on the
      target CPU. This is achieved by temporarily setting the affinity of the
      calling user space thread to the requested CPU and reset it to the original
      affinity afterwards.
      
      That's racy vs. concurrent affinity settings for that thread resulting in
      code executing on the wrong CPU and overwriting the new affinity setting.
      
      Replace it by using work_on_cpu() which guarantees to run the code on the
      requested CPU.
      
      Protection against CPU hotplug is not required as the open sysfs file
      already prevents the removal from the CPU offline callback. Using the
      hotplug protected version would actually be wrong because it would deadlock
      against a CPU hotplug operation of the CPU associated to the sysfs file in
      progress.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      Cc: fenghua.yu@intel.com
      Cc: tony.luck@intel.com
      Cc: herbert@gondor.apana.org.au
      Cc: rjw@rjwysocki.net
      Cc: peterz@infradead.org
      Cc: benh@kernel.crashing.org
      Cc: bigeasy@linutronix.de
      Cc: jiangshanlai@gmail.com
      Cc: sparclinux@vger.kernel.org
      Cc: viresh.kumar@linaro.org
      Cc: mpe@ellerman.id.au
      Cc: tj@kernel.org
      Cc: lenb@kernel.org
      Link: http://lkml.kernel.org/r/alpine.DEB.2.20.1704131001270.2408@nanosSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      ea875ec9
    • N
      sparc/time: Set ->min_delta_ticks and ->max_delta_ticks · 7fd53424
      Nicolai Stange 提交于
      In preparation for making the clockevents core NTP correction aware,
      all clockevent device drivers must set ->min_delta_ticks and
      ->max_delta_ticks rather than ->min_delta_ns and ->max_delta_ns: a
      clockevent device's rate is going to change dynamically and thus, the
      ratio of ns to ticks ceases to stay invariant.
      
      Make the sparc arch's clockevent drivers initialize these fields properly.
      
      This patch alone doesn't introduce any change in functionality as the
      clockevents core still looks exclusively at the (untouched) ->min_delta_ns
      and ->max_delta_ns. As soon as this has changed, a followup patch will
      purge the initialization of ->min_delta_ns and ->max_delta_ns from these
      drivers.
      
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Richard Cochran <richardcochran@gmail.com>
      Cc: Prarit Bhargava <prarit@redhat.com>
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: sparclinux@vger.kernel.org
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      Signed-off-by: NNicolai Stange <nicstange@gmail.com>
      Signed-off-by: NJohn Stultz <john.stultz@linaro.org>
      7fd53424
  16. 08 4月, 2017 1 次提交
  17. 07 4月, 2017 3 次提交