1. 31 1月, 2018 12 次提交
  2. 27 1月, 2018 3 次提交
  3. 11 1月, 2018 1 次提交
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      PCI/DPC: Fix shared interrupt handling · aa6ca5a9
      Alex Williamson 提交于
      DPC supports shared interrupts, but it plays very loosely with testing
      whether the interrupt is generated by DPC before generating spurious log
      messages, such as:
      
        dpc 0000:10:01.2:pcie010: DPC containment event, status:0x1f00 source:0x0000
      
      Testing the status register for zero or -1 is not sufficient when the
      device supports the RP PIO First Error Pointer register.  Change this to
      test whether the interrupt is enabled in the control register, retaining
      the device present test, and that the status reports the interrupt as
      signaled and DPC is triggered, clearing as a spurious interrupt otherwise.
      
      Additionally, since the interrupt is actually serviced by a workqueue,
      disable the interrupt in the control register until that completes or else
      we may never see it execute due to further incoming interrupts.  A software
      generated DPC floods the system otherwise.
      Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      Signed-off-by: NBjorn Helgaas <helgaas@kernel.org>
      Reviewed-by: NKeith Busch <keith.busch@intel.com>
      aa6ca5a9
  4. 18 12月, 2017 9 次提交
  5. 17 12月, 2017 15 次提交