Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openanolis
cloud-kernel
提交
ff72b7a6
cloud-kernel
项目概览
openanolis
/
cloud-kernel
1 年多 前同步成功
通知
160
Star
36
Fork
7
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
10
列表
看板
标记
里程碑
合并请求
2
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
cloud-kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
10
Issue
10
列表
看板
标记
里程碑
合并请求
2
合并请求
2
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
提交
ff72b7a6
编写于
6月 07, 2007
作者:
R
Ralf Baechle
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[MIPS] Fix smp barriers in test_and_{change,clear,set}_bit
Signed-off-by:
N
Ralf Baechle
<
ralf@linux-mips.org
>
上级
e10e0cc8
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
19 addition
and
32 deletion
+19
-32
include/asm-mips/bitops.h
include/asm-mips/bitops.h
+19
-32
未找到文件。
include/asm-mips/bitops.h
浏览文件 @
ff72b7a6
...
...
@@ -238,10 +238,11 @@ static inline int test_and_set_bit(unsigned long nr,
volatile
unsigned
long
*
addr
)
{
unsigned
short
bit
=
nr
&
SZLONG_MASK
;
unsigned
long
res
;
if
(
cpu_has_llsc
&&
R10000_LLSC_WAR
)
{
unsigned
long
*
m
=
((
unsigned
long
*
)
addr
)
+
(
nr
>>
SZLONG_LOG
);
unsigned
long
temp
,
res
;
unsigned
long
temp
;
__asm__
__volatile__
(
" .set mips3
\n
"
...
...
@@ -254,11 +255,9 @@ static inline int test_and_set_bit(unsigned long nr,
:
"=&r"
(
temp
),
"=m"
(
*
m
),
"=&r"
(
res
)
:
"r"
(
1UL
<<
bit
),
"m"
(
*
m
)
:
"memory"
);
return
res
!=
0
;
}
else
if
(
cpu_has_llsc
)
{
unsigned
long
*
m
=
((
unsigned
long
*
)
addr
)
+
(
nr
>>
SZLONG_LOG
);
unsigned
long
temp
,
res
;
unsigned
long
temp
;
__asm__
__volatile__
(
" .set push
\n
"
...
...
@@ -277,25 +276,22 @@ static inline int test_and_set_bit(unsigned long nr,
:
"=&r"
(
temp
),
"=m"
(
*
m
),
"=&r"
(
res
)
:
"r"
(
1UL
<<
bit
),
"m"
(
*
m
)
:
"memory"
);
return
res
!=
0
;
}
else
{
volatile
unsigned
long
*
a
=
addr
;
unsigned
long
mask
;
int
retval
;
unsigned
long
flags
;
a
+=
nr
>>
SZLONG_LOG
;
mask
=
1UL
<<
bit
;
raw_local_irq_save
(
flags
);
re
tval
=
(
mask
&
*
a
)
!=
0
;
re
s
=
(
mask
&
*
a
)
;
*
a
|=
mask
;
raw_local_irq_restore
(
flags
);
return
retval
;
}
smp_mb
();
return
res
!=
0
;
}
/*
...
...
@@ -310,6 +306,7 @@ static inline int test_and_clear_bit(unsigned long nr,
volatile
unsigned
long
*
addr
)
{
unsigned
short
bit
=
nr
&
SZLONG_MASK
;
unsigned
long
res
;
if
(
cpu_has_llsc
&&
R10000_LLSC_WAR
)
{
unsigned
long
*
m
=
((
unsigned
long
*
)
addr
)
+
(
nr
>>
SZLONG_LOG
);
...
...
@@ -327,12 +324,10 @@ static inline int test_and_clear_bit(unsigned long nr,
:
"=&r"
(
temp
),
"=m"
(
*
m
),
"=&r"
(
res
)
:
"r"
(
1UL
<<
bit
),
"m"
(
*
m
)
:
"memory"
);
return
res
!=
0
;
#ifdef CONFIG_CPU_MIPSR2
}
else
if
(
__builtin_constant_p
(
nr
))
{
unsigned
long
*
m
=
((
unsigned
long
*
)
addr
)
+
(
nr
>>
SZLONG_LOG
);
unsigned
long
temp
,
res
;
unsigned
long
temp
;
__asm__
__volatile__
(
"1: "
__LL
"%0, %1 # test_and_clear_bit
\n
"
...
...
@@ -346,12 +341,10 @@ static inline int test_and_clear_bit(unsigned long nr,
:
"=&r"
(
temp
),
"=m"
(
*
m
),
"=&r"
(
res
)
:
"ri"
(
bit
),
"m"
(
*
m
)
:
"memory"
);
return
res
;
#endif
}
else
if
(
cpu_has_llsc
)
{
unsigned
long
*
m
=
((
unsigned
long
*
)
addr
)
+
(
nr
>>
SZLONG_LOG
);
unsigned
long
temp
,
res
;
unsigned
long
temp
;
__asm__
__volatile__
(
" .set push
\n
"
...
...
@@ -371,25 +364,22 @@ static inline int test_and_clear_bit(unsigned long nr,
:
"=&r"
(
temp
),
"=m"
(
*
m
),
"=&r"
(
res
)
:
"r"
(
1UL
<<
bit
),
"m"
(
*
m
)
:
"memory"
);
return
res
!=
0
;
}
else
{
volatile
unsigned
long
*
a
=
addr
;
unsigned
long
mask
;
int
retval
;
unsigned
long
flags
;
a
+=
nr
>>
SZLONG_LOG
;
mask
=
1UL
<<
bit
;
raw_local_irq_save
(
flags
);
re
tval
=
(
mask
&
*
a
)
!=
0
;
re
s
=
(
mask
&
*
a
)
;
*
a
&=
~
mask
;
raw_local_irq_restore
(
flags
);
return
retval
;
}
smp_mb
();
return
res
!=
0
;
}
/*
...
...
@@ -404,10 +394,11 @@ static inline int test_and_change_bit(unsigned long nr,
volatile
unsigned
long
*
addr
)
{
unsigned
short
bit
=
nr
&
SZLONG_MASK
;
unsigned
long
res
;
if
(
cpu_has_llsc
&&
R10000_LLSC_WAR
)
{
unsigned
long
*
m
=
((
unsigned
long
*
)
addr
)
+
(
nr
>>
SZLONG_LOG
);
unsigned
long
temp
,
res
;
unsigned
long
temp
;
__asm__
__volatile__
(
" .set mips3
\n
"
...
...
@@ -420,11 +411,9 @@ static inline int test_and_change_bit(unsigned long nr,
:
"=&r"
(
temp
),
"=m"
(
*
m
),
"=&r"
(
res
)
:
"r"
(
1UL
<<
bit
),
"m"
(
*
m
)
:
"memory"
);
return
res
!=
0
;
}
else
if
(
cpu_has_llsc
)
{
unsigned
long
*
m
=
((
unsigned
long
*
)
addr
)
+
(
nr
>>
SZLONG_LOG
);
unsigned
long
temp
,
res
;
unsigned
long
temp
;
__asm__
__volatile__
(
" .set push
\n
"
...
...
@@ -443,24 +432,22 @@ static inline int test_and_change_bit(unsigned long nr,
:
"=&r"
(
temp
),
"=m"
(
*
m
),
"=&r"
(
res
)
:
"r"
(
1UL
<<
bit
),
"m"
(
*
m
)
:
"memory"
);
return
res
!=
0
;
}
else
{
volatile
unsigned
long
*
a
=
addr
;
unsigned
long
mask
,
retval
;
unsigned
long
mask
;
unsigned
long
flags
;
a
+=
nr
>>
SZLONG_LOG
;
mask
=
1UL
<<
bit
;
raw_local_irq_save
(
flags
);
re
tval
=
(
mask
&
*
a
)
!=
0
;
re
s
=
(
mask
&
*
a
)
;
*
a
^=
mask
;
raw_local_irq_restore
(
flags
);
return
retval
;
}
smp_mb
();
return
res
!=
0
;
}
#include <asm-generic/bitops/non-atomic.h>
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录