提交 fe6adc19 编写于 作者: S Sakari Ailus 提交者: Mauro Carvalho Chehab

[media] omap3isp: Add lane configuration to platform data

Add lane configuration (order of clock and data lane) to platform data on
both CCP2 and CSI-2.
Signed-off-by: NSakari Ailus <sakari.ailus@iki.fi>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
上级 da39257f
......@@ -27,22 +27,11 @@
#ifndef OMAP3_ISP_CSI_PHY_H
#define OMAP3_ISP_CSI_PHY_H
#include <media/omap3isp.h>
struct isp_csi2_device;
struct regulator;
struct csiphy_lane {
u8 pos;
u8 pol;
};
#define ISP_CSIPHY2_NUM_DATA_LANES 2
#define ISP_CSIPHY1_NUM_DATA_LANES 1
struct isp_csiphy_lanes_cfg {
struct csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
struct csiphy_lane clk;
};
struct isp_csiphy_dphy_cfg {
u8 ths_term;
u8 ths_settle;
......
......@@ -90,6 +90,29 @@ enum {
ISP_CCP2_MODE_CCP2 = 1,
};
/**
* struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
* @pos: position of the lane
* @pol: polarity of the lane
*/
struct isp_csiphy_lane {
u8 pos;
u8 pol;
};
#define ISP_CSIPHY1_NUM_DATA_LANES 1
#define ISP_CSIPHY2_NUM_DATA_LANES 2
/**
* struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
* @data: Configuration of one or two data lanes
* @clk: Clock lane configuration
*/
struct isp_csiphy_lanes_cfg {
struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
struct isp_csiphy_lane clk;
};
/**
* struct isp_ccp2_platform_data - CCP2 interface platform data
* @strobe_clk_pol: Strobe/clock polarity
......@@ -109,6 +132,7 @@ struct isp_ccp2_platform_data {
unsigned int ccp2_mode:1;
unsigned int phy_layer:1;
unsigned int vpclk_div:2;
struct isp_csiphy_lanes_cfg lanecfg;
};
/**
......@@ -119,6 +143,7 @@ struct isp_ccp2_platform_data {
struct isp_csi2_platform_data {
unsigned crc:1;
unsigned vpclk_div:2;
struct isp_csiphy_lanes_cfg lanecfg;
};
struct isp_subdev_i2c_board_info {
......
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