clk: mediatek: Disable tuner_en before change PLL rate
commit be17ca6ac76a5cfd07cc3a0397dd05d6929fcbbb upstream. PLLs with tuner_en bit, such as APLL1, need to disable tuner_en before apply new frequency settings, or the new frequency settings (pcw) will not be applied. The tuner_en bit will be disabled during changing PLL rate and be restored after new settings applied. Fixes: e2f744a8 (clk: mediatek: Add MT2712 clock support) Cc: <stable@vger.kernel.org> Signed-off-by: NOwen Chen <owen.chen@mediatek.com> Signed-off-by: NWeiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: NJames Liao <jamesjj.liao@mediatek.com> Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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