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faeede8c
编写于
4月 08, 2011
作者:
M
Mark Brown
浏览文件
操作
浏览文件
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差异文件
Merge branch 'for-2.6.39' into for-2.6.40
上级
b39e2855
1b877cb5
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
23 addition
and
15 deletion
+23
-15
sound/soc/codecs/wm8903.c
sound/soc/codecs/wm8903.c
+23
-15
未找到文件。
sound/soc/codecs/wm8903.c
浏览文件 @
faeede8c
...
...
@@ -247,8 +247,6 @@ static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int re
case
WM8903_REVISION_NUMBER
:
case
WM8903_INTERRUPT_STATUS_1
:
case
WM8903_WRITE_SEQUENCER_4
:
case
WM8903_POWER_MANAGEMENT_3
:
case
WM8903_POWER_MANAGEMENT_2
:
case
WM8903_DC_SERVO_READBACK_1
:
case
WM8903_DC_SERVO_READBACK_2
:
case
WM8903_DC_SERVO_READBACK_3
:
...
...
@@ -875,34 +873,40 @@ SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
SND_SOC_DAPM_MIXER
(
"Right Speaker Mixer"
,
WM8903_POWER_MANAGEMENT_4
,
0
,
0
,
right_speaker_mixer
,
ARRAY_SIZE
(
right_speaker_mixer
)),
SND_SOC_DAPM_PGA_S
(
"Left Headphone Output PGA"
,
0
,
WM8903_
ANALOGUE_HP_0
,
4
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"Right Headphone Output PGA"
,
0
,
WM8903_
ANALOGUE_HP_0
,
SND_SOC_DAPM_PGA_S
(
"Left Headphone Output PGA"
,
0
,
WM8903_
POWER_MANAGEMENT_2
,
1
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"Right Headphone Output PGA"
,
0
,
WM8903_
POWER_MANAGEMENT_2
,
0
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"Left Line Output PGA"
,
0
,
WM8903_
ANALOGUE_LINEOUT_0
,
4
,
0
,
SND_SOC_DAPM_PGA_S
(
"Left Line Output PGA"
,
0
,
WM8903_
POWER_MANAGEMENT_3
,
1
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"Right Line Output PGA"
,
0
,
WM8903_
ANALOGUE_LINEOUT_0
,
0
,
0
,
SND_SOC_DAPM_PGA_S
(
"Right Line Output PGA"
,
0
,
WM8903_
POWER_MANAGEMENT_3
,
0
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPL_RMV_SHORT"
,
4
,
WM8903_ANALOGUE_HP_0
,
7
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPL_ENA_OUTP"
,
3
,
WM8903_ANALOGUE_HP_0
,
6
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPL_ENA_DLY"
,
1
,
WM8903_ANALOGUE_HP_0
,
5
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPL_ENA_DLY"
,
2
,
WM8903_ANALOGUE_HP_0
,
5
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPL_ENA"
,
1
,
WM8903_ANALOGUE_HP_0
,
4
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPR_RMV_SHORT"
,
4
,
WM8903_ANALOGUE_HP_0
,
3
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPR_ENA_OUTP"
,
3
,
WM8903_ANALOGUE_HP_0
,
2
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPR_ENA_DLY"
,
1
,
WM8903_ANALOGUE_HP_0
,
1
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPR_ENA_DLY"
,
2
,
WM8903_ANALOGUE_HP_0
,
1
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"HPR_ENA"
,
1
,
WM8903_ANALOGUE_HP_0
,
0
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"LINEOUTL_RMV_SHORT"
,
4
,
WM8903_ANALOGUE_LINEOUT_0
,
7
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"LINEOUTL_ENA_OUTP"
,
3
,
WM8903_ANALOGUE_LINEOUT_0
,
6
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"LINEOUTL_ENA_DLY"
,
1
,
WM8903_ANALOGUE_LINEOUT_0
,
5
,
0
,
SND_SOC_DAPM_PGA_S
(
"LINEOUTL_ENA_DLY"
,
2
,
WM8903_ANALOGUE_LINEOUT_0
,
5
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"LINEOUTL_ENA"
,
1
,
WM8903_ANALOGUE_LINEOUT_0
,
4
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"LINEOUTR_RMV_SHORT"
,
4
,
WM8903_ANALOGUE_LINEOUT_0
,
3
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"LINEOUTR_ENA_OUTP"
,
3
,
WM8903_ANALOGUE_LINEOUT_0
,
2
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"LINEOUTR_ENA_DLY"
,
1
,
WM8903_ANALOGUE_LINEOUT_0
,
1
,
0
,
SND_SOC_DAPM_PGA_S
(
"LINEOUTR_ENA_DLY"
,
2
,
WM8903_ANALOGUE_LINEOUT_0
,
1
,
0
,
NULL
,
0
),
SND_SOC_DAPM_PGA_S
(
"LINEOUTR_ENA"
,
1
,
WM8903_ANALOGUE_LINEOUT_0
,
0
,
0
,
NULL
,
0
),
SND_SOC_DAPM_SUPPLY
(
"DCS Master"
,
WM8903_DC_SERVO_0
,
4
,
0
,
NULL
,
0
),
...
...
@@ -1037,10 +1041,14 @@ static const struct snd_soc_dapm_route wm8903_intercon[] = {
{
"Left Speaker PGA"
,
NULL
,
"Left Speaker Mixer"
},
{
"Right Speaker PGA"
,
NULL
,
"Right Speaker Mixer"
},
{
"HPL_ENA_DLY"
,
NULL
,
"Left Headphone Output PGA"
},
{
"HPR_ENA_DLY"
,
NULL
,
"Right Headphone Output PGA"
},
{
"LINEOUTL_ENA_DLY"
,
NULL
,
"Left Line Output PGA"
},
{
"LINEOUTR_ENA_DLY"
,
NULL
,
"Right Line Output PGA"
},
{
"HPL_ENA"
,
NULL
,
"Left Headphone Output PGA"
},
{
"HPR_ENA"
,
NULL
,
"Right Headphone Output PGA"
},
{
"HPL_ENA_DLY"
,
NULL
,
"HPL_ENA"
},
{
"HPR_ENA_DLY"
,
NULL
,
"HPR_ENA"
},
{
"LINEOUTL_ENA"
,
NULL
,
"Left Line Output PGA"
},
{
"LINEOUTR_ENA"
,
NULL
,
"Right Line Output PGA"
},
{
"LINEOUTL_ENA_DLY"
,
NULL
,
"LINEOUTL_ENA"
},
{
"LINEOUTR_ENA_DLY"
,
NULL
,
"LINEOUTR_ENA"
},
{
"HPL_DCS"
,
NULL
,
"DCS Master"
},
{
"HPR_DCS"
,
NULL
,
"DCS Master"
},
...
...
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