提交 f7e504c7 编写于 作者: M Matt Porter 提交者: Felipe Balbi

usb: gadget: s3c-hsotg: get phy bus width from phy subsystem

Adds support for querying the phy bus width from the generic phy
subsystem. Configure UTMI bus width in GUSBCFG based on this value.
Signed-off-by: NMatt Porter <mporter@linaro.org>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>
上级 74084844
......@@ -146,6 +146,7 @@ struct s3c_hsotg_ep {
* @regs: The memory area mapped for accessing registers.
* @irq: The IRQ number we are using
* @supplies: Definition of USB power supplies
* @phyif: PHY interface width
* @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
* @num_of_eps: Number of available EPs (excluding EP0)
* @debug_root: root directrory for debugfs.
......@@ -174,6 +175,7 @@ struct s3c_hsotg {
struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
u32 phyif;
unsigned int dedicated_fifos:1;
unsigned char num_of_eps;
......@@ -2288,7 +2290,7 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
*/
/* set the PLL on, remove the HNP/SRP and set the PHY */
writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) |
writel(hsotg->phyif | GUSBCFG_TOutCal(7) |
(0x5 << 10), hsotg->regs + GUSBCFG);
s3c_hsotg_init_fifo(hsotg);
......@@ -3646,6 +3648,16 @@ static int s3c_hsotg_probe(struct platform_device *pdev)
goto err_supplies;
}
/* Set default UTMI width */
hsotg->phyif = GUSBCFG_PHYIf16;
/*
* If using the generic PHY framework, check if the PHY bus
* width is 8-bit and set the phyif appropriately.
*/
if (hsotg->phy && (phy_get_bus_width(phy) == 8))
hsotg->phyif = GUSBCFG_PHYIf8;
if (hsotg->phy)
phy_init(hsotg->phy);
......
......@@ -55,6 +55,7 @@
#define GUSBCFG_HNPCap (1 << 9)
#define GUSBCFG_SRPCap (1 << 8)
#define GUSBCFG_PHYIf16 (1 << 3)
#define GUSBCFG_PHYIf8 (0 << 3)
#define GUSBCFG_TOutCal_MASK (0x7 << 0)
#define GUSBCFG_TOutCal_SHIFT (0)
#define GUSBCFG_TOutCal_LIMIT (0x7)
......
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