Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openanolis
cloud-kernel
提交
f66f9bdf
cloud-kernel
项目概览
openanolis
/
cloud-kernel
1 年多 前同步成功
通知
161
Star
36
Fork
7
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
10
列表
看板
标记
里程碑
合并请求
2
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
cloud-kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
10
Issue
10
列表
看板
标记
里程碑
合并请求
2
合并请求
2
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
提交
f66f9bdf
编写于
12年前
作者:
A
Arnd Bergmann
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'lpc32xx/drivers' into next/drivers
上级
f6175f22
36225dec
变更
11
隐藏空白更改
内联
并排
Showing
11 changed file
with
389 addition
and
117 deletion
+389
-117
arch/arm/configs/lpc32xx_defconfig
arch/arm/configs/lpc32xx_defconfig
+145
-0
arch/arm/mach-lpc32xx/Kconfig
arch/arm/mach-lpc32xx/Kconfig
+25
-0
arch/arm/mach-lpc32xx/clock.c
arch/arm/mach-lpc32xx/clock.c
+84
-65
arch/arm/mach-lpc32xx/common.c
arch/arm/mach-lpc32xx/common.c
+47
-0
arch/arm/mach-lpc32xx/common.h
arch/arm/mach-lpc32xx/common.h
+3
-3
arch/arm/mach-lpc32xx/include/mach/board.h
arch/arm/mach-lpc32xx/include/mach/board.h
+24
-0
arch/arm/mach-lpc32xx/include/mach/platform.h
arch/arm/mach-lpc32xx/include/mach/platform.h
+27
-24
arch/arm/mach-lpc32xx/irq.c
arch/arm/mach-lpc32xx/irq.c
+4
-0
arch/arm/mach-lpc32xx/phy3250.c
arch/arm/mach-lpc32xx/phy3250.c
+5
-0
arch/arm/mach-lpc32xx/pm.c
arch/arm/mach-lpc32xx/pm.c
+1
-1
arch/arm/mach-lpc32xx/timer.c
arch/arm/mach-lpc32xx/timer.c
+24
-24
未找到文件。
arch/arm/configs/lpc32xx_defconfig
0 → 100644
浏览文件 @
f66f9bdf
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_LPC32XX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
CONFIG_CPU_IDLE=y
CONFIG_FPE_NWFPE=y
CONFIG_VFP=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_AOUT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_MUSEUM_IDS=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_MISC_DEVICES=y
CONFIG_EEPROM_AT25=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_PHYLIB=y
CONFIG_SMSC_PHY=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_LPC32XX=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PNX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_PNX4008_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_DYNAMIC_MINORS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_SOC=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_LIBUSUAL=y
CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_LPC32XX=y
CONFIG_EXT2_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_ANSI_CPRNG=y
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/Kconfig
浏览文件 @
f66f9bdf
...
...
@@ -29,5 +29,30 @@ config ARCH_LPC32XX_UART6_SELECT
endmenu
menu "LPC32XX chip components"
config ARCH_LPC32XX_IRAM_FOR_NET
bool "Use IRAM for network buffers"
default y
help
Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as
network buffer. If the total combined required buffer sizes is
larger than the size of IRAM, then SDRAM will be used instead.
This can be enabled safely if the IRAM is not intended for other
uses.
config ARCH_LPC32XX_MII_SUPPORT
bool "Check to enable MII support or leave disabled for RMII support"
help
Say Y here to enable MII support, or N for RMII support. Regardless of
which support is selected, the ethernet interface driver needs to be
selected in the device driver networking section.
The PHY3250 reference board uses RMII, so users of this board should
say N.
endmenu
endif
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/clock.c
浏览文件 @
f66f9bdf
...
...
@@ -82,10 +82,12 @@
* will also impact the individual peripheral rates.
*/
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/amba/bus.h>
...
...
@@ -97,9 +99,12 @@
#include "clock.h"
#include "common.h"
static
DEFINE_SPINLOCK
(
global_clkregs_lock
);
static
int
usb_pll_enable
,
usb_pll_valid
;
static
struct
clk
clk_armpll
;
static
struct
clk
clk_usbpll
;
static
DEFINE_MUTEX
(
clkm_lock
);
/*
* Post divider values for PLLs based on selected register value
...
...
@@ -127,7 +132,7 @@ static struct clk osc_32KHz = {
static
int
local_pll397_enable
(
struct
clk
*
clk
,
int
enable
)
{
u32
reg
;
unsigned
long
timeout
=
1
+
msecs_to_jiffies
(
10
);
unsigned
long
timeout
=
jiffies
+
msecs_to_jiffies
(
10
);
reg
=
__raw_readl
(
LPC32XX_CLKPWR_PLL397_CTRL
);
...
...
@@ -142,7 +147,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
/* Wait for PLL397 lock */
while
(((
__raw_readl
(
LPC32XX_CLKPWR_PLL397_CTRL
)
&
LPC32XX_CLKPWR_SYSCTRL_PLL397_STS
)
==
0
)
&&
(
timeout
>
jiffies
))
time_before
(
jiffies
,
timeout
))
cpu_relax
();
if
((
__raw_readl
(
LPC32XX_CLKPWR_PLL397_CTRL
)
&
...
...
@@ -156,7 +161,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
static
int
local_oscmain_enable
(
struct
clk
*
clk
,
int
enable
)
{
u32
reg
;
unsigned
long
timeout
=
1
+
msecs_to_jiffies
(
10
);
unsigned
long
timeout
=
jiffies
+
msecs_to_jiffies
(
10
);
reg
=
__raw_readl
(
LPC32XX_CLKPWR_MAIN_OSC_CTRL
);
...
...
@@ -171,7 +176,7 @@ static int local_oscmain_enable(struct clk *clk, int enable)
/* Wait for main oscillator to start */
while
(((
__raw_readl
(
LPC32XX_CLKPWR_MAIN_OSC_CTRL
)
&
LPC32XX_CLKPWR_MOSC_DISABLE
)
!=
0
)
&&
(
timeout
>
jiffies
))
time_before
(
jiffies
,
timeout
))
cpu_relax
();
if
((
__raw_readl
(
LPC32XX_CLKPWR_MAIN_OSC_CTRL
)
&
...
...
@@ -382,30 +387,62 @@ static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
static
int
local_usbpll_enable
(
struct
clk
*
clk
,
int
enable
)
{
u32
reg
;
int
ret
=
-
ENODEV
;
unsigned
long
timeout
=
1
+
msecs_to_jiffies
(
1
0
);
int
ret
=
0
;
unsigned
long
timeout
=
jiffies
+
msecs_to_jiffies
(
2
0
);
reg
=
__raw_readl
(
LPC32XX_CLKPWR_USB_CTRL
);
if
(
enable
==
0
)
{
reg
&=
~
(
LPC32XX_CLKPWR_USBCTRL_CLK_EN1
|
LPC32XX_CLKPWR_USBCTRL_CLK_EN2
);
__raw_writel
(
reg
,
LPC32XX_CLKPWR_USB_CTRL
);
}
else
if
(
reg
&
LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP
)
{
__raw_writel
(
reg
&
~
(
LPC32XX_CLKPWR_USBCTRL_CLK_EN2
|
LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP
),
LPC32XX_CLKPWR_USB_CTRL
);
__raw_writel
(
reg
&
~
LPC32XX_CLKPWR_USBCTRL_CLK_EN1
,
LPC32XX_CLKPWR_USB_CTRL
);
if
(
enable
&&
usb_pll_valid
&&
usb_pll_enable
)
{
ret
=
-
ENODEV
;
/*
* If the PLL rate has been previously set, then the rate
* in the PLL register is valid and can be enabled here.
* Otherwise, it needs to be enabled as part of setrate.
*/
/*
* Gate clock into PLL
*/
reg
|=
LPC32XX_CLKPWR_USBCTRL_CLK_EN1
;
__raw_writel
(
reg
,
LPC32XX_CLKPWR_USB_CTRL
);
/* Wait for PLL lock */
while
((
timeout
>
jiffies
)
&
(
ret
==
-
ENODEV
))
{
/*
* Enable PLL
*/
reg
|=
LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP
;
__raw_writel
(
reg
,
LPC32XX_CLKPWR_USB_CTRL
);
/*
* Wait for PLL to lock
*/
while
(
time_before
(
jiffies
,
timeout
)
&&
(
ret
==
-
ENODEV
))
{
reg
=
__raw_readl
(
LPC32XX_CLKPWR_USB_CTRL
);
if
(
reg
&
LPC32XX_CLKPWR_USBCTRL_PLL_STS
)
ret
=
0
;
else
udelay
(
10
);
}
/*
* Gate clock from PLL if PLL is locked
*/
if
(
ret
==
0
)
{
reg
|=
LPC32XX_CLKPWR_USBCTRL_CLK_EN2
;
__raw_writel
(
reg
,
LPC32XX_CLKPWR_USB_CTRL
);
__raw_writel
(
reg
|
LPC32XX_CLKPWR_USBCTRL_CLK_EN2
,
LPC32XX_CLKPWR_USB_CTRL
);
}
else
{
__raw_writel
(
reg
&
~
(
LPC32XX_CLKPWR_USBCTRL_CLK_EN1
|
LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP
),
LPC32XX_CLKPWR_USB_CTRL
);
}
}
else
if
((
enable
==
0
)
&&
usb_pll_valid
&&
usb_pll_enable
)
{
usb_pll_valid
=
0
;
usb_pll_enable
=
0
;
}
return
ret
;
...
...
@@ -423,7 +460,7 @@ static unsigned long local_usbpll_round_rate(struct clk *clk,
*/
rate
=
rate
*
1000
;
clkin
=
clk
->
parent
->
rate
;
clkin
=
clk
->
get_rate
(
clk
)
;
usbdiv
=
(
__raw_readl
(
LPC32XX_CLKPWR_USBCLK_PDIV
)
&
LPC32XX_CLKPWR_USBPDIV_PLL_MASK
)
+
1
;
clkin
=
clkin
/
usbdiv
;
...
...
@@ -437,7 +474,8 @@ static unsigned long local_usbpll_round_rate(struct clk *clk,
static
int
local_usbpll_set_rate
(
struct
clk
*
clk
,
unsigned
long
rate
)
{
u32
clkin
,
reg
,
usbdiv
;
int
ret
=
-
ENODEV
;
u32
clkin
,
usbdiv
;
struct
clk_pll_setup
pllsetup
;
/*
...
...
@@ -446,7 +484,7 @@ static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
*/
rate
=
rate
*
1000
;
clkin
=
clk
->
get_rate
(
clk
);
clkin
=
clk
->
get_rate
(
clk
->
parent
);
usbdiv
=
(
__raw_readl
(
LPC32XX_CLKPWR_USBCLK_PDIV
)
&
LPC32XX_CLKPWR_USBPDIV_PLL_MASK
)
+
1
;
clkin
=
clkin
/
usbdiv
;
...
...
@@ -455,22 +493,25 @@ static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
if
(
local_clk_find_pll_cfg
(
clkin
,
rate
,
&
pllsetup
)
==
0
)
return
-
EINVAL
;
/*
* Disable PLL clocks during PLL change
*/
local_usbpll_enable
(
clk
,
0
);
reg
=
__raw_readl
(
LPC32XX_CLKPWR_USB_CTRL
);
reg
|=
LPC32XX_CLKPWR_USBCTRL_CLK_EN1
;
__raw_writel
(
reg
,
LPC32XX_CLKPWR_USB_CTRL
);
pllsetup
.
analog_on
=
1
;
pllsetup
.
analog_on
=
0
;
local_clk_usbpll_setup
(
&
pllsetup
);
clk
->
rate
=
clk_check_pll_setup
(
clkin
,
&
pllsetup
);
/*
* Start USB PLL and check PLL status
*/
reg
=
__raw_readl
(
LPC32XX_CLKPWR_USB_CTRL
);
reg
|=
LPC32XX_CLKPWR_USBCTRL_CLK_EN2
;
__raw_writel
(
reg
,
LPC32XX_CLKPWR_USB_CTRL
);
usb_pll_valid
=
1
;
usb_pll_enable
=
1
;
return
0
;
ret
=
local_usbpll_enable
(
clk
,
1
);
if
(
ret
>=
0
)
clk
->
rate
=
clk_check_pll_setup
(
clkin
,
&
pllsetup
);
return
ret
;
}
static
struct
clk
clk_usbpll
=
{
...
...
@@ -926,20 +967,8 @@ static struct clk clk_lcd = {
.
enable_mask
=
LPC32XX_CLKPWR_LCDCTRL_CLK_EN
,
};
static
inline
void
clk_lock
(
void
)
{
mutex_lock
(
&
clkm_lock
);
}
static
inline
void
clk_unlock
(
void
)
{
mutex_unlock
(
&
clkm_lock
);
}
static
void
local_clk_disable
(
struct
clk
*
clk
)
{
WARN_ON
(
clk
->
usecount
==
0
);
/* Don't attempt to disable clock if it has no users */
if
(
clk
->
usecount
>
0
)
{
clk
->
usecount
--
;
...
...
@@ -982,10 +1011,11 @@ static int local_clk_enable(struct clk *clk)
int
clk_enable
(
struct
clk
*
clk
)
{
int
ret
;
unsigned
long
flags
;
clk_lock
(
);
spin_lock_irqsave
(
&
global_clkregs_lock
,
flags
);
ret
=
local_clk_enable
(
clk
);
clk_unlock
(
);
spin_unlock_irqrestore
(
&
global_clkregs_lock
,
flags
);
return
ret
;
}
...
...
@@ -996,9 +1026,11 @@ EXPORT_SYMBOL(clk_enable);
*/
void
clk_disable
(
struct
clk
*
clk
)
{
clk_lock
();
unsigned
long
flags
;
spin_lock_irqsave
(
&
global_clkregs_lock
,
flags
);
local_clk_disable
(
clk
);
clk_unlock
(
);
spin_unlock_irqrestore
(
&
global_clkregs_lock
,
flags
);
}
EXPORT_SYMBOL
(
clk_disable
);
...
...
@@ -1007,13 +1039,7 @@ EXPORT_SYMBOL(clk_disable);
*/
unsigned
long
clk_get_rate
(
struct
clk
*
clk
)
{
unsigned
long
rate
;
clk_lock
();
rate
=
clk
->
get_rate
(
clk
);
clk_unlock
();
return
rate
;
return
clk
->
get_rate
(
clk
);
}
EXPORT_SYMBOL
(
clk_get_rate
);
...
...
@@ -1029,11 +1055,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
* the actual rate set as part of the peripheral dividers
* instead of high level clock control
*/
if
(
clk
->
set_rate
)
{
clk_lock
();
if
(
clk
->
set_rate
)
ret
=
clk
->
set_rate
(
clk
,
rate
);
clk_unlock
();
}
return
ret
;
}
...
...
@@ -1044,15 +1067,11 @@ EXPORT_SYMBOL(clk_set_rate);
*/
long
clk_round_rate
(
struct
clk
*
clk
,
unsigned
long
rate
)
{
clk_lock
();
if
(
clk
->
round_rate
)
rate
=
clk
->
round_rate
(
clk
,
rate
);
else
rate
=
clk
->
get_rate
(
clk
);
clk_unlock
();
return
rate
;
}
EXPORT_SYMBOL
(
clk_round_rate
);
...
...
@@ -1110,12 +1129,12 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK
(
"dev:ssp1"
,
NULL
,
clk_ssp1
)
_REGISTER_CLOCK
(
"lpc32xx_keys.0"
,
NULL
,
clk_kscan
)
_REGISTER_CLOCK
(
"lpc32xx-nand.0"
,
"nand_ck"
,
clk_nand
)
_REGISTER_CLOCK
(
NULL
,
"i2s0_ck"
,
clk_i2s0
)
_REGISTER_CLOCK
(
NULL
,
"i2s1_ck"
,
clk_i2s1
)
_REGISTER_CLOCK
(
"lpc32xx-adc"
,
NULL
,
clk_adc
)
_REGISTER_CLOCK
(
"tbd"
,
"i2s0_ck"
,
clk_i2s0
)
_REGISTER_CLOCK
(
"tbd"
,
"i2s1_ck"
,
clk_i2s1
)
_REGISTER_CLOCK
(
"ts-lpc32xx"
,
NULL
,
clk_tsc
)
_REGISTER_CLOCK
(
"dev:mmc0"
,
"MCLK"
,
clk_mmc
)
_REGISTER_CLOCK
(
"lpc-
net
.0"
,
NULL
,
clk_net
)
_REGISTER_CLOCK
(
"dev:mmc0"
,
NULL
,
clk_mmc
)
_REGISTER_CLOCK
(
"lpc-
eth
.0"
,
NULL
,
clk_net
)
_REGISTER_CLOCK
(
"dev:clcd"
,
NULL
,
clk_lcd
)
_REGISTER_CLOCK
(
"lpc32xx_udc"
,
"ck_usbd"
,
clk_usbd
)
_REGISTER_CLOCK
(
"lpc32xx_rtc"
,
NULL
,
clk_rtc
)
...
...
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/common.c
浏览文件 @
f66f9bdf
...
...
@@ -159,6 +159,53 @@ struct platform_device lpc32xx_adc_device = {
.
resource
=
adc_resources
,
};
/*
* USB support
*/
/* The dmamask must be set for OHCI to work */
static
u64
ohci_dmamask
=
~
(
u32
)
0
;
static
struct
resource
ohci_resources
[]
=
{
{
.
start
=
IO_ADDRESS
(
LPC32XX_USB_BASE
),
.
end
=
IO_ADDRESS
(
LPC32XX_USB_BASE
+
0x100
-
1
),
.
flags
=
IORESOURCE_MEM
,
},
{
.
start
=
IRQ_LPC32XX_USB_HOST
,
.
flags
=
IORESOURCE_IRQ
,
},
};
struct
platform_device
lpc32xx_ohci_device
=
{
.
name
=
"usb-ohci"
,
.
id
=
-
1
,
.
dev
=
{
.
dma_mask
=
&
ohci_dmamask
,
.
coherent_dma_mask
=
0xFFFFFFFF
,
},
.
num_resources
=
ARRAY_SIZE
(
ohci_resources
),
.
resource
=
ohci_resources
,
};
/*
* Network Support
*/
static
struct
resource
net_resources
[]
=
{
[
0
]
=
DEFINE_RES_MEM
(
LPC32XX_ETHERNET_BASE
,
SZ_4K
),
[
1
]
=
DEFINE_RES_MEM
(
LPC32XX_IRAM_BASE
,
SZ_128K
),
[
2
]
=
DEFINE_RES_IRQ
(
IRQ_LPC32XX_ETHERNET
),
};
static
u64
lpc32xx_mac_dma_mask
=
0xffffffffUL
;
struct
platform_device
lpc32xx_net_device
=
{
.
name
=
"lpc-eth"
,
.
id
=
0
,
.
dev
=
{
.
dma_mask
=
&
lpc32xx_mac_dma_mask
,
.
coherent_dma_mask
=
0xffffffffUL
,
},
.
num_resources
=
ARRAY_SIZE
(
net_resources
),
.
resource
=
net_resources
,
};
/*
* Returns the unique ID for the device
*/
...
...
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/common.h
浏览文件 @
f66f9bdf
...
...
@@ -19,6 +19,7 @@
#ifndef __LPC32XX_COMMON_H
#define __LPC32XX_COMMON_H
#include <mach/board.h>
#include <linux/platform_device.h>
/*
...
...
@@ -31,6 +32,8 @@ extern struct platform_device lpc32xx_i2c2_device;
extern
struct
platform_device
lpc32xx_tsc_device
;
extern
struct
platform_device
lpc32xx_adc_device
;
extern
struct
platform_device
lpc32xx_rtc_device
;
extern
struct
platform_device
lpc32xx_ohci_device
;
extern
struct
platform_device
lpc32xx_net_device
;
/*
* Other arch specific structures and functions
...
...
@@ -66,9 +69,6 @@ extern u32 clk_get_pclk_div(void);
*/
extern
void
lpc32xx_get_uid
(
u32
devid
[
4
]);
extern
void
lpc32xx_watchdog_reset
(
void
);
extern
u32
lpc32xx_return_iram_size
(
void
);
/*
* Pointers used for sizing and copying suspend function data
*/
...
...
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/include/mach/board.h
0 → 100644
浏览文件 @
f66f9bdf
/*
* arm/arch/mach-lpc32xx/include/mach/board.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_BOARD_H
#define __ASM_ARCH_BOARD_H
extern
u32
lpc32xx_return_iram_size
(
void
);
#endif
/* __ASM_ARCH_BOARD_H */
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/include/mach/platform.h
浏览文件 @
f66f9bdf
...
...
@@ -591,42 +591,42 @@
/*
* Timer/counter register offsets
*/
#define L
CP
32XX_TIMER_IR(x) io_p2v((x) + 0x00)
#define L
CP
32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
#define L
CP
32XX_TIMER_TC(x) io_p2v((x) + 0x08)
#define L
CP
32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
#define L
CP
32XX_TIMER_PC(x) io_p2v((x) + 0x10)
#define L
CP
32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
#define L
CP
32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
#define L
CP
32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
#define L
CP
32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
#define L
CP
32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
#define L
CP
32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
#define L
CP
32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
#define L
CP
32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
#define L
CP
32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
#define L
CP
32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
#define L
CP
32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
#define L
CP
32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
#define L
PC
32XX_TIMER_IR(x) io_p2v((x) + 0x00)
#define L
PC
32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
#define L
PC
32XX_TIMER_TC(x) io_p2v((x) + 0x08)
#define L
PC
32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
#define L
PC
32XX_TIMER_PC(x) io_p2v((x) + 0x10)
#define L
PC
32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
#define L
PC
32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
#define L
PC
32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
#define L
PC
32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
#define L
PC
32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
#define L
PC
32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
#define L
PC
32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
#define L
PC
32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
#define L
PC
32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
#define L
PC
32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
#define L
PC
32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
#define L
PC
32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
/*
* ir register definitions
*/
#define L
CP
32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
#define L
CP
32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
#define L
PC
32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
#define L
PC
32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
/*
* tcr register definitions
*/
#define L
CP
32XX_TIMER_CNTR_TCR_EN 0x1
#define L
CP
32XX_TIMER_CNTR_TCR_RESET 0x2
#define L
PC
32XX_TIMER_CNTR_TCR_EN 0x1
#define L
PC
32XX_TIMER_CNTR_TCR_RESET 0x2
/*
* mcr register definitions
*/
#define L
CP
32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
#define L
CP
32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
#define L
CP
32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
#define L
PC
32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
#define L
PC
32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
#define L
PC
32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
/*
* Standard UART register offsets
...
...
@@ -690,5 +690,8 @@
#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
#endif
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/irq.c
浏览文件 @
f66f9bdf
...
...
@@ -150,6 +150,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
.
event_group
=
&
lpc32xx_event_int_regs
,
.
mask
=
LPC32XX_CLKPWR_INTSRC_KEY_BIT
,
},
[
IRQ_LPC32XX_ETHERNET
]
=
{
.
event_group
=
&
lpc32xx_event_int_regs
,
.
mask
=
LPC32XX_CLKPWR_INTSRC_MAC_BIT
,
},
[
IRQ_LPC32XX_USB_OTG_ATX
]
=
{
.
event_group
=
&
lpc32xx_event_int_regs
,
.
mask
=
LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT
,
...
...
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/phy3250.c
浏览文件 @
f66f9bdf
...
...
@@ -37,6 +37,7 @@
#include <mach/hardware.h>
#include <mach/platform.h>
#include <mach/board.h>
#include <mach/gpio-lpc32xx.h>
#include "common.h"
...
...
@@ -247,12 +248,16 @@ static struct platform_device lpc32xx_gpio_led_device = {
};
static
struct
platform_device
*
phy3250_devs
[]
__initdata
=
{
&
lpc32xx_rtc_device
,
&
lpc32xx_tsc_device
,
&
lpc32xx_i2c0_device
,
&
lpc32xx_i2c1_device
,
&
lpc32xx_i2c2_device
,
&
lpc32xx_watchdog_device
,
&
lpc32xx_gpio_led_device
,
&
lpc32xx_adc_device
,
&
lpc32xx_ohci_device
,
&
lpc32xx_net_device
,
};
static
struct
amba_device
*
amba_devs
[]
__initdata
=
{
...
...
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/pm.c
浏览文件 @
f66f9bdf
...
...
@@ -13,7 +13,7 @@
/*
* LPC32XX CPU and system power management
*
* The L
CP
32XX has three CPU modes for controlling system power: run,
* The L
PC
32XX has three CPU modes for controlling system power: run,
* direct-run, and halt modes. When switching between halt and run modes,
* the CPU transistions through direct-run mode. For Linux, direct-run
* mode is not used in normal operation. Halt mode is used when the
...
...
This diff is collapsed.
Click to expand it.
arch/arm/mach-lpc32xx/timer.c
浏览文件 @
f66f9bdf
...
...
@@ -34,11 +34,11 @@
static
int
lpc32xx_clkevt_next_event
(
unsigned
long
delta
,
struct
clock_event_device
*
dev
)
{
__raw_writel
(
L
CP
32XX_TIMER_CNTR_TCR_RESET
,
L
CP
32XX_TIMER_TCR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
delta
,
L
CP
32XX_TIMER_PR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
L
CP
32XX_TIMER_CNTR_TCR_EN
,
L
CP
32XX_TIMER_TCR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
L
PC
32XX_TIMER_CNTR_TCR_RESET
,
L
PC
32XX_TIMER_TCR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
delta
,
L
PC
32XX_TIMER_PR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
L
PC
32XX_TIMER_CNTR_TCR_EN
,
L
PC
32XX_TIMER_TCR
(
LPC32XX_TIMER0_BASE
));
return
0
;
}
...
...
@@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
* disable the timer to wait for the first call to
* set_next_event().
*/
__raw_writel
(
0
,
L
CP
32XX_TIMER_TCR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
0
,
L
PC
32XX_TIMER_TCR
(
LPC32XX_TIMER0_BASE
));
break
;
case
CLOCK_EVT_MODE_UNUSED
:
...
...
@@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
struct
clock_event_device
*
evt
=
&
lpc32xx_clkevt
;
/* Clear match */
__raw_writel
(
L
CP
32XX_TIMER_CNTR_MTCH_BIT
(
0
),
L
CP
32XX_TIMER_IR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
L
PC
32XX_TIMER_CNTR_MTCH_BIT
(
0
),
L
PC
32XX_TIMER_IR
(
LPC32XX_TIMER0_BASE
));
evt
->
event_handler
(
evt
);
...
...
@@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(void)
clkrate
=
clkrate
/
clk_get_pclk_div
();
/* Initial timer setup */
__raw_writel
(
0
,
L
CP
32XX_TIMER_TCR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
L
CP
32XX_TIMER_CNTR_MTCH_BIT
(
0
),
L
CP
32XX_TIMER_IR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
1
,
L
CP
32XX_TIMER_MR0
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
L
CP
32XX_TIMER_CNTR_MCR_MTCH
(
0
)
|
L
CP
32XX_TIMER_CNTR_MCR_STOP
(
0
)
|
L
CP
32XX_TIMER_CNTR_MCR_RESET
(
0
),
L
CP
32XX_TIMER_MCR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
0
,
L
PC
32XX_TIMER_TCR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
L
PC
32XX_TIMER_CNTR_MTCH_BIT
(
0
),
L
PC
32XX_TIMER_IR
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
1
,
L
PC
32XX_TIMER_MR0
(
LPC32XX_TIMER0_BASE
));
__raw_writel
(
L
PC
32XX_TIMER_CNTR_MCR_MTCH
(
0
)
|
L
PC
32XX_TIMER_CNTR_MCR_STOP
(
0
)
|
L
PC
32XX_TIMER_CNTR_MCR_RESET
(
0
),
L
PC
32XX_TIMER_MCR
(
LPC32XX_TIMER0_BASE
));
/* Setup tick interrupt */
setup_irq
(
IRQ_LPC32XX_TIMER0
,
&
lpc32xx_timer_irq
);
...
...
@@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(void)
clockevents_register_device
(
&
lpc32xx_clkevt
);
/* Use timer1 as clock source. */
__raw_writel
(
L
CP
32XX_TIMER_CNTR_TCR_RESET
,
L
CP
32XX_TIMER_TCR
(
LPC32XX_TIMER1_BASE
));
__raw_writel
(
0
,
L
CP
32XX_TIMER_PR
(
LPC32XX_TIMER1_BASE
));
__raw_writel
(
0
,
L
CP
32XX_TIMER_MCR
(
LPC32XX_TIMER1_BASE
));
__raw_writel
(
L
CP
32XX_TIMER_CNTR_TCR_EN
,
L
CP
32XX_TIMER_TCR
(
LPC32XX_TIMER1_BASE
));
clocksource_mmio_init
(
L
CP
32XX_TIMER_TC
(
LPC32XX_TIMER1_BASE
),
__raw_writel
(
L
PC
32XX_TIMER_CNTR_TCR_RESET
,
L
PC
32XX_TIMER_TCR
(
LPC32XX_TIMER1_BASE
));
__raw_writel
(
0
,
L
PC
32XX_TIMER_PR
(
LPC32XX_TIMER1_BASE
));
__raw_writel
(
0
,
L
PC
32XX_TIMER_MCR
(
LPC32XX_TIMER1_BASE
));
__raw_writel
(
L
PC
32XX_TIMER_CNTR_TCR_EN
,
L
PC
32XX_TIMER_TCR
(
LPC32XX_TIMER1_BASE
));
clocksource_mmio_init
(
L
PC
32XX_TIMER_TC
(
LPC32XX_TIMER1_BASE
),
"lpc32xx_clksrc"
,
clkrate
,
300
,
32
,
clocksource_mmio_readl_up
);
}
...
...
This diff is collapsed.
Click to expand it.
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录
新手
引导
客服
返回
顶部