提交 f3d73f36 编写于 作者: S Sukumar Ghorai 提交者: Tony Lindgren

omap3: nand: ecc layout select from board file

This patch makes it possible to select sw or hw (different layout options)
ecc scheme supported by omap nand driver.
Signed-off-by: NVimal Singh <vimalsingh@ti.com>
Signed-off-by: NSukumar Ghorai <s-ghorai@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
上级 317379a9
...@@ -148,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, ...@@ -148,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
board_nand_data.nr_parts = nr_parts; board_nand_data.nr_parts = nr_parts;
board_nand_data.devsize = nand_type; board_nand_data.devsize = nand_type;
board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
gpmc_nand_init(&board_nand_data); gpmc_nand_init(&board_nand_data);
} }
......
...@@ -86,6 +86,12 @@ ...@@ -86,6 +86,12 @@
#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
enum omap_ecc {
/* 1-bit ecc: stored at end of spare area */
OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
};
/* /*
* Note that all values in this struct are in nanoseconds except sync_clk * Note that all values in this struct are in nanoseconds except sync_clk
* (which is in picoseconds), while the register values are in gpmc_fck cycles. * (which is in picoseconds), while the register values are in gpmc_fck cycles.
......
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <plat/gpmc.h>
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
enum nand_io { enum nand_io {
...@@ -31,6 +32,7 @@ struct omap_nand_platform_data { ...@@ -31,6 +32,7 @@ struct omap_nand_platform_data {
enum nand_io xfer_type; enum nand_io xfer_type;
unsigned long phys_base; unsigned long phys_base;
int devsize; int devsize;
enum omap_ecc ecc_opt;
}; };
/* minimum size for IO mapping */ /* minimum size for IO mapping */
......
...@@ -626,8 +626,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) ...@@ -626,8 +626,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
return 0; return 0;
} }
#ifdef CONFIG_MTD_NAND_OMAP_HWECC
/** /**
* gen_true_ecc - This function will generate true ECC value * gen_true_ecc - This function will generate true ECC value
* @ecc_buf: buffer to store ecc code * @ecc_buf: buffer to store ecc code
...@@ -847,8 +845,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) ...@@ -847,8 +845,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
} }
#endif
/** /**
* omap_wait - wait until the command is done * omap_wait - wait until the command is done
* @mtd: MTD device structure * @mtd: MTD device structure
...@@ -1038,17 +1034,17 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) ...@@ -1038,17 +1034,17 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
info->nand.verify_buf = omap_verify_buf; info->nand.verify_buf = omap_verify_buf;
#ifdef CONFIG_MTD_NAND_OMAP_HWECC /* selsect the ecc type */
info->nand.ecc.bytes = 3; if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
info->nand.ecc.size = 512; info->nand.ecc.mode = NAND_ECC_SOFT;
info->nand.ecc.calculate = omap_calculate_ecc; else if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) {
info->nand.ecc.hwctl = omap_enable_hwecc; info->nand.ecc.bytes = 3;
info->nand.ecc.correct = omap_correct_data; info->nand.ecc.size = 512;
info->nand.ecc.mode = NAND_ECC_HW; info->nand.ecc.calculate = omap_calculate_ecc;
info->nand.ecc.hwctl = omap_enable_hwecc;
#else info->nand.ecc.correct = omap_correct_data;
info->nand.ecc.mode = NAND_ECC_SOFT; info->nand.ecc.mode = NAND_ECC_HW;
#endif }
/* DIP switches on some boards change between 8 and 16 bit /* DIP switches on some boards change between 8 and 16 bit
* bus widths for flash. Try the other width if the first try fails. * bus widths for flash. Try the other width if the first try fails.
......
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