ARM: OMAP: USB: Change omap USB code to use omap_read/write instead of __REG

Change omap USB code to use omap_read/write instead of __REG for multi-omap

Cc: David Brownell <david-b@pacbell.net>
Cc: linux-usb@vger.kernel.org
Cc: i2c@lm-sensors.org
Signed-off-by: NTony Lindgren <tony@atomide.com>

arch/arm/mach-omap1/board-osk.c

@@ -546,7 +546,10 @@ static void __init osk_init(void)
 	platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
 	omap_board_config = osk_config;
 	omap_board_config_size = ARRAY_SIZE(osk_config);
-	USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+
+	l = omap_readl(USB_TRANSCEIVER_CTRL);
+	l |= (3 << 1);
+	omap_writel(l, USB_TRANSCEIVER_CTRL);
 
 	/* irq for tps65010 chip */
 	/* bootloader effectively does:  omap_cfg_reg(U19_1610_MPUIO1); */

arch/arm/plat-omap/usb.c

-/*
+ /*
  * arch/arm/plat-omap/usb.c -- platform level USB initialization
  *
  * Copyright (C) 2004 Texas Instruments, Inc.
@@ -156,8 +156,12 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 
 	if (nwires == 0) {
 		if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+			u32 l;
+
 			/* pulldown D+/D- */
-			USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1);
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l &= ~(3 << 1);
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
 		}
 		return 0;
 	}
@@ -171,6 +175,8 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 
 	/* internal transceiver (unavailable on 17xx, 24xx) */
 	if (!cpu_class_is_omap2() && nwires == 2) {
+		u32 l;
+
 		// omap_cfg_reg(P9_USB_DP);
 		// omap_cfg_reg(R8_USB_DM);
 
@@ -185,9 +191,11 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 		 *  - OTG support on this port not yet written
 		 */
 
-		USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4);
+		l = omap_readl(USB_TRANSCEIVER_CTRL);
+		l &= ~(7 << 4);
 		if (!is_device)
-			USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
+			l |= (3 << 1);
+		omap_writel(l, USB_TRANSCEIVER_CTRL);
 
 		return 3 << 16;
 	}
@@ -217,8 +225,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 	 * with VBUS switching and overcurrent detection.
 	 */
 
-	if (cpu_class_is_omap1() && nwires != 6)
-		USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+	if (cpu_class_is_omap1() && nwires != 6) {
+		u32 l;
+
+		l = omap_readl(USB_TRANSCEIVER_CTRL);
+		l &= ~CONF_USB2_UNI_R;
+		omap_writel(l, USB_TRANSCEIVER_CTRL);
+	}
 
 	switch (nwires) {
 	case 3:
@@ -238,9 +251,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 			omap_cfg_reg(K20_24XX_USB0_VM);
 			omap2_usb_devconf_set(0, USB_UNIDIR);
 		} else {
+			u32 l;
+
 			omap_cfg_reg(AA9_USB0_VP);
 			omap_cfg_reg(R9_USB0_VM);
-			USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l |= CONF_USB2_UNI_R;
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
 		}
 		break;
 	default:
@@ -254,8 +271,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
 {
 	u32	syscon1 = 0;
 
-	if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
-		USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
+	if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+		u32 l;
+
+		l = omap_readl(USB_TRANSCEIVER_CTRL);
+		l &= ~CONF_USB1_UNI_R;
+		omap_writel(l, USB_TRANSCEIVER_CTRL);
+	}
 	if (cpu_is_omap24xx())
 		omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
 
@@ -316,8 +338,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
 		syscon1 = 3;
 		omap_cfg_reg(USB1_VP);
 		omap_cfg_reg(USB1_VM);
-		if (!cpu_is_omap15xx())
-			USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R;
+		if (!cpu_is_omap15xx()) {
+			u32 l;
+
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l |= CONF_USB1_UNI_R;
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
+		}
 		break;
 	default:
 bad:
@@ -340,8 +367,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
 	if (alt_pingroup || nwires == 0)
 		return 0;
 
-	if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
-		USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
+	if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+		u32 l;
+
+		l = omap_readl(USB_TRANSCEIVER_CTRL);
+		l &= ~CONF_USB2_UNI_R;
+		omap_writel(l, USB_TRANSCEIVER_CTRL);
+	}
 
 	/* external transceiver */
 	if (cpu_is_omap15xx()) {
@@ -410,9 +442,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
 			omap_cfg_reg(USB2_VP);
 			omap_cfg_reg(USB2_VM);
 		} else {
+			u32 l;
+
 			omap_cfg_reg(AA9_USB2_VP);
 			omap_cfg_reg(R9_USB2_VM);
-			USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l |= CONF_USB2_UNI_R;
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
 		}
 		break;
 	default:
@@ -531,10 +567,6 @@ static struct platform_device otg_device = {
 
 /*-------------------------------------------------------------------------*/
 
-#define ULPD_CLOCK_CTRL_REG	__REG16(ULPD_CLOCK_CTRL)
-#define ULPD_SOFT_REQ_REG	__REG16(ULPD_SOFT_REQ)
-
-
 // FIXME correct answer depends on hmc_mode,
 // as does (on omap1) any nonzero value for config->otg port number
 #ifdef	CONFIG_USB_GADGET_OMAP
@@ -550,17 +582,17 @@ static struct platform_device otg_device = {
 void __init
 omap_otg_init(struct omap_usb_config *config)
 {
-	u32		syscon = OTG_SYSCON_1_REG & 0xffff;
+	u32		syscon;
 	int		status;
 	int		alt_pingroup = 0;
 
 	/* NOTE:  no bus or clock setup (yet?) */
 
-	syscon = OTG_SYSCON_1_REG & 0xffff;
+	syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
 	if (!(syscon & OTG_RESET_DONE))
 		pr_debug("USB resets not complete?\n");
 
-	// OTG_IRQ_EN_REG = 0;
+	//omap_writew(0, OTG_IRQ_EN);
 
 	/* pin muxing and transceiver pinouts */
 	if (config->pins[0] > 2)	/* alt pingroup 2 */
@@ -568,8 +600,8 @@ omap_otg_init(struct omap_usb_config *config)
 	syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
 	syscon |= omap_usb1_init(config->pins[1]);
 	syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
-	pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
-	OTG_SYSCON_1_REG = syscon;
+	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+	omap_writel(syscon, OTG_SYSCON_1);
 
 	syscon = config->hmc_mode;
 	syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
@@ -578,9 +610,10 @@ omap_otg_init(struct omap_usb_config *config)
 		syscon |= OTG_EN;
 #endif
 	if (cpu_class_is_omap1())
-		pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG);
-	pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon);
-	OTG_SYSCON_2_REG = syscon;
+		pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
+			 omap_readl(USB_TRANSCEIVER_CTRL));
+	pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
+	omap_writel(syscon, OTG_SYSCON_2);
 
 	printk("USB: hmc %d", config->hmc_mode);
 	if (!alt_pingroup)
@@ -597,12 +630,19 @@ omap_otg_init(struct omap_usb_config *config)
 	printk("\n");
 
 	if (cpu_class_is_omap1()) {
+		u16 w;
+
 		/* leave USB clocks/controllers off until needed */
-		ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ;
-		ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN;
-		ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK;
+		w = omap_readw(ULPD_SOFT_REQ);
+		w &= ~SOFT_USB_CLK_REQ;
+		omap_writew(w, ULPD_SOFT_REQ);
+
+		w = omap_readw(ULPD_CLOCK_CTRL);
+		w &= ~USB_MCLK_EN;
+		w |= DIS_USB_PVCI_CLK;
+		omap_writew(w, ULPD_CLOCK_CTRL);
 	}
-	syscon = OTG_SYSCON_1_REG;
+	syscon = omap_readl(OTG_SYSCON_1);
 	syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
 
 #ifdef	CONFIG_USB_GADGET_OMAP
@@ -639,8 +679,8 @@ omap_otg_init(struct omap_usb_config *config)
 			pr_debug("can't register OTG device, %d\n", status);
 	}
 #endif
-	pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
-	OTG_SYSCON_1_REG = syscon;
+	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+	omap_writel(syscon, OTG_SYSCON_1);
 
 	status = 0;
 }
@@ -653,18 +693,19 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
 
 #ifdef	CONFIG_ARCH_OMAP15XX
 
-#define ULPD_DPLL_CTRL_REG	__REG16(ULPD_DPLL_CTRL)
+/* ULPD_DPLL_CTRL */
 #define DPLL_IOB		(1 << 13)
 #define DPLL_PLL_ENABLE		(1 << 4)
 #define DPLL_LOCK		(1 << 0)
 
-#define ULPD_APLL_CTRL_REG	__REG16(ULPD_APLL_CTRL)
+/* ULPD_APLL_CTRL */
 #define APLL_NDPLL_SWITCH	(1 << 0)
 
 
 static void __init omap_1510_usb_init(struct omap_usb_config *config)
 {
 	unsigned int val;
+	u16 w;
 
 	omap_usb0_init(config->pins[0], is_usb0_device(config));
 	omap_usb1_init(config->pins[1]);
@@ -685,12 +726,22 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
 	printk("\n");
 
 	/* use DPLL for 48 MHz function clock */
-	pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG,
-			ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG);
-	ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH;
-	ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE;
-	ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
-	while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK))
+	pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
+			omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
+
+	w = omap_readw(ULPD_APLL_CTRL);
+	w &= ~APLL_NDPLL_SWITCH;
+	omap_writew(w, ULPD_APLL_CTRL);
+
+	w = omap_readw(ULPD_DPLL_CTRL);
+	w |= DPLL_IOB | DPLL_PLL_ENABLE;
+	omap_writew(w, ULPD_DPLL_CTRL);
+
+	w = omap_readw(ULPD_SOFT_REQ);
+	w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
+	omap_writew(w, ULPD_SOFT_REQ);
+
+	while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
 		cpu_relax();
 
 #ifdef	CONFIG_USB_GADGET_OMAP

drivers/i2c/chips/isp1301_omap.c

@@ -72,7 +72,7 @@ struct isp1301 {
 };
 
 
-/* bits in OTG_CTRL_REG */
+/* bits in OTG_CTRL */
 
 #define	OTG_XCEIV_OUTPUTS \
 	(OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
@@ -186,8 +186,8 @@ isp1301_clear_bits(struct isp1301 *isp, u8 reg, u8 bits)
 
 /* operational registers */
 #define	ISP1301_MODE_CONTROL_1		0x04	/* u8 read, set, +1 clear */
-#	define	MC1_SPEED_REG		(1 << 0)
-#	define	MC1_SUSPEND_REG		(1 << 1)
+#	define	MC1_SPEED		(1 << 0)
+#	define	MC1_SUSPEND		(1 << 1)
 #	define	MC1_DAT_SE0		(1 << 2)
 #	define	MC1_TRANSPARENT		(1 << 3)
 #	define	MC1_BDIS_ACON_EN	(1 << 4)
@@ -274,7 +274,7 @@ static void power_down(struct isp1301 *isp)
 	isp->otg.state = OTG_STATE_UNDEFINED;
 
 	// isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
-	isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG);
+	isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
 
 	isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_ID_PULLDOWN);
 	isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
@@ -283,7 +283,7 @@ static void power_down(struct isp1301 *isp)
 static void power_up(struct isp1301 *isp)
 {
 	// isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
-	isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG);
+	isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
 
 	/* do this only when cpu is driving transceiver,
 	 * so host won't see a low speed device...
@@ -360,6 +360,8 @@ isp1301_defer_work(struct isp1301 *isp, int work)
 /* called from irq handlers */
 static void a_idle(struct isp1301 *isp, const char *tag)
 {
+	u32 l;
+
 	if (isp->otg.state == OTG_STATE_A_IDLE)
 		return;
 
@@ -373,13 +375,17 @@ static void a_idle(struct isp1301 *isp, const char *tag)
 		gadget_suspend(isp);
 	}
 	isp->otg.state = OTG_STATE_A_IDLE;
-	isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+	l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+	omap_writel(l, OTG_CTRL);
+	isp->last_otg_ctrl = l;
 	pr_debug("  --> %s/%s\n", state_name(isp), tag);
 }
 
 /* called from irq handlers */
 static void b_idle(struct isp1301 *isp, const char *tag)
 {
+	u32 l;
+
 	if (isp->otg.state == OTG_STATE_B_IDLE)
 		return;
 
@@ -393,7 +399,9 @@ static void b_idle(struct isp1301 *isp, const char *tag)
 		gadget_suspend(isp);
 	}
 	isp->otg.state = OTG_STATE_B_IDLE;
-	isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+	l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+	omap_writel(l, OTG_CTRL);
+	isp->last_otg_ctrl = l;
 	pr_debug("  --> %s/%s\n", state_name(isp), tag);
 }
 
@@ -406,7 +414,7 @@ dump_regs(struct isp1301 *isp, const char *label)
 	u8	src = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE);
 
 	pr_debug("otg: %06x, %s %s, otg/%02x stat/%02x.%02x\n",
-		OTG_CTRL_REG, label, state_name(isp),
+		omap_readl(OTG_CTRL), label, state_name(isp),
 		ctrl, status, src);
 	/* mode control and irq enables don't change much */
 #endif
@@ -429,7 +437,7 @@ dump_regs(struct isp1301 *isp, const char *label)
 static void check_state(struct isp1301 *isp, const char *tag)
 {
 	enum usb_otg_state	state = OTG_STATE_UNDEFINED;
-	u8			fsm = OTG_TEST_REG & 0x0ff;
+	u8			fsm = omap_readw(OTG_TEST) & 0x0ff;
 	unsigned		extra = 0;
 
 	switch (fsm) {
@@ -494,7 +502,8 @@ static void check_state(struct isp1301 *isp, const char *tag)
 	if (isp->otg.state == state && !extra)
 		return;
 	pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag,
-		state_string(state), fsm, state_name(isp), OTG_CTRL_REG);
+		state_string(state), fsm, state_name(isp),
+		omap_readl(OTG_CTRL));
 }
 
 #else
@@ -508,10 +517,11 @@ static void update_otg1(struct isp1301 *isp, u8 int_src)
 {
 	u32	otg_ctrl;
 
-	otg_ctrl = OTG_CTRL_REG
-			& OTG_CTRL_MASK
-			& ~OTG_XCEIV_INPUTS
-			& ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD);
+	otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+	otg_ctrl &= ~OTG_XCEIV_INPUTS;
+	otg_ctrl &= ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD);
+
+
 	if (int_src & INTR_SESS_VLD)
 		otg_ctrl |= OTG_ASESSVLD;
 	else if (isp->otg.state == OTG_STATE_A_WAIT_VFALL) {
@@ -534,7 +544,7 @@ static void update_otg1(struct isp1301 *isp, u8 int_src)
 			return;
 		}
 	}
-	OTG_CTRL_REG = otg_ctrl;
+	omap_writel(otg_ctrl, OTG_CTRL);
 }
 
 /* outputs from ISP1301_OTG_STATUS */
@@ -542,15 +552,14 @@ static void update_otg2(struct isp1301 *isp, u8 otg_status)
 {
 	u32	otg_ctrl;
 
-	otg_ctrl = OTG_CTRL_REG
-			& OTG_CTRL_MASK
-			& ~OTG_XCEIV_INPUTS
-			& ~(OTG_BSESSVLD|OTG_BSESSEND);
+	otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+	otg_ctrl &= ~OTG_XCEIV_INPUTS;
+	otg_ctrl &= ~(OTG_BSESSVLD | OTG_BSESSEND);
 	if (otg_status & OTG_B_SESS_VLD)
 		otg_ctrl |= OTG_BSESSVLD;
 	else if (otg_status & OTG_B_SESS_END)
 		otg_ctrl |= OTG_BSESSEND;
-	OTG_CTRL_REG = otg_ctrl;
+	omap_writel(otg_ctrl, OTG_CTRL);
 }
 
 /* inputs going to ISP1301 */
@@ -559,7 +568,7 @@ static void otg_update_isp(struct isp1301 *isp)
 	u32	otg_ctrl, otg_change;
 	u8	set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP;
 
-	otg_ctrl = OTG_CTRL_REG;
+	otg_ctrl = omap_readl(OTG_CTRL);
 	otg_change = otg_ctrl ^ isp->last_otg_ctrl;
 	isp->last_otg_ctrl = otg_ctrl;
 	otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS;
@@ -639,6 +648,8 @@ static void otg_update_isp(struct isp1301 *isp)
 
 	/* HNP switch to host or peripheral; and SRP */
 	if (otg_change & OTG_PULLUP) {
+		u32 l;
+
 		switch (isp->otg.state) {
 		case OTG_STATE_B_IDLE:
 			if (clr & OTG1_DP_PULLUP)
@@ -655,7 +666,9 @@ static void otg_update_isp(struct isp1301 *isp)
 		default:
 			break;
 		}
-		OTG_CTRL_REG |= OTG_PULLUP;
+		l = omap_readl(OTG_CTRL);
+		l |= OTG_PULLUP;
+		omap_writel(l, OTG_CTRL);
 	}
 
 	check_state(isp, __func__);
@@ -664,20 +677,20 @@ static void otg_update_isp(struct isp1301 *isp)
 
 static irqreturn_t omap_otg_irq(int irq, void *_isp)
 {
-	u16		otg_irq = OTG_IRQ_SRC_REG;
+	u16		otg_irq = omap_readw(OTG_IRQ_SRC);
 	u32		otg_ctrl;
 	int		ret = IRQ_NONE;
 	struct isp1301	*isp = _isp;
 
 	/* update ISP1301 transciever from OTG controller */
 	if (otg_irq & OPRT_CHG) {
-		OTG_IRQ_SRC_REG = OPRT_CHG;
+		omap_writew(OPRT_CHG, OTG_IRQ_SRC);
 		isp1301_defer_work(isp, WORK_UPDATE_ISP);
 		ret = IRQ_HANDLED;
 
 	/* SRP to become b_peripheral failed */
 	} else if (otg_irq & B_SRP_TMROUT) {
-		pr_debug("otg: B_SRP_TIMEOUT, %06x\n", OTG_CTRL_REG);
+		pr_debug("otg: B_SRP_TIMEOUT, %06x\n", omap_readl(OTG_CTRL));
 		notresponding(isp);
 
 		/* gadget drivers that care should monitor all kinds of
@@ -687,31 +700,31 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
 		if (isp->otg.state == OTG_STATE_B_SRP_INIT)
 			b_idle(isp, "srp_timeout");
 
-		OTG_IRQ_SRC_REG = B_SRP_TMROUT;
+		omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
 		ret = IRQ_HANDLED;
 
 	/* HNP to become b_host failed */
 	} else if (otg_irq & B_HNP_FAIL) {
 		pr_debug("otg: %s B_HNP_FAIL, %06x\n",
-				state_name(isp), OTG_CTRL_REG);
+				state_name(isp), omap_readl(OTG_CTRL));
 		notresponding(isp);
 
-		otg_ctrl = OTG_CTRL_REG;
+		otg_ctrl = omap_readl(OTG_CTRL);
 		otg_ctrl |= OTG_BUSDROP;
 		otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
-		OTG_CTRL_REG = otg_ctrl;
+		omap_writel(otg_ctrl, OTG_CTRL);
 
 		/* subset of b_peripheral()... */
 		isp->otg.state = OTG_STATE_B_PERIPHERAL;
 		pr_debug("  --> b_peripheral\n");
 
-		OTG_IRQ_SRC_REG = B_HNP_FAIL;
+		omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
 		ret = IRQ_HANDLED;
 
 	/* detect SRP from B-device ... */
 	} else if (otg_irq & A_SRP_DETECT) {
 		pr_debug("otg: %s SRP_DETECT, %06x\n",
-				state_name(isp), OTG_CTRL_REG);
+				state_name(isp), omap_readl(OTG_CTRL));
 
 		isp1301_defer_work(isp, WORK_UPDATE_OTG);
 		switch (isp->otg.state) {
@@ -719,49 +732,49 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
 			if (!isp->otg.host)
 				break;
 			isp1301_defer_work(isp, WORK_HOST_RESUME);
-			otg_ctrl = OTG_CTRL_REG;
+			otg_ctrl = omap_readl(OTG_CTRL);
 			otg_ctrl |= OTG_A_BUSREQ;
 			otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
 					& ~OTG_XCEIV_INPUTS
 					& OTG_CTRL_MASK;
-			OTG_CTRL_REG = otg_ctrl;
+			omap_writel(otg_ctrl, OTG_CTRL);
 			break;
 		default:
 			break;
 		}
 
-		OTG_IRQ_SRC_REG = A_SRP_DETECT;
+		omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
 		ret = IRQ_HANDLED;
 
 	/* timer expired:  T(a_wait_bcon) and maybe T(a_wait_vrise)
 	 * we don't track them separately
 	 */
 	} else if (otg_irq & A_REQ_TMROUT) {
-		otg_ctrl = OTG_CTRL_REG;
+		otg_ctrl = omap_readl(OTG_CTRL);
 		pr_info("otg: BCON_TMOUT from %s, %06x\n",
 				state_name(isp), otg_ctrl);
 		notresponding(isp);
 
 		otg_ctrl |= OTG_BUSDROP;
 		otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
-		OTG_CTRL_REG = otg_ctrl;
+		omap_writel(otg_ctrl, OTG_CTRL);
 		isp->otg.state = OTG_STATE_A_WAIT_VFALL;
 
-		OTG_IRQ_SRC_REG = A_REQ_TMROUT;
+		omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
 		ret = IRQ_HANDLED;
 
 	/* A-supplied voltage fell too low; overcurrent */
 	} else if (otg_irq & A_VBUS_ERR) {
-		otg_ctrl = OTG_CTRL_REG;
+		otg_ctrl = omap_readl(OTG_CTRL);
 		printk(KERN_ERR "otg: %s, VBUS_ERR %04x ctrl %06x\n",
 			state_name(isp), otg_irq, otg_ctrl);
 
 		otg_ctrl |= OTG_BUSDROP;
 		otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
-		OTG_CTRL_REG = otg_ctrl;
+		omap_writel(otg_ctrl, OTG_CTRL);
 		isp->otg.state = OTG_STATE_A_VBUS_ERR;
 
-		OTG_IRQ_SRC_REG = A_VBUS_ERR;
+		omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
 		ret = IRQ_HANDLED;
 
 	/* switch driver; the transciever code activates it,
@@ -770,7 +783,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
 	} else if (otg_irq & DRIVER_SWITCH) {
 		int	kick = 0;
 
-		otg_ctrl = OTG_CTRL_REG;
+		otg_ctrl = omap_readl(OTG_CTRL);
 		printk(KERN_NOTICE "otg: %s, SWITCH to %s, ctrl %06x\n",
 				state_name(isp),
 				(otg_ctrl & OTG_DRIVER_SEL)
@@ -793,7 +806,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
 		} else {
 			if (!(otg_ctrl & OTG_ID)) {
 				otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
-				OTG_CTRL_REG = otg_ctrl | OTG_A_BUSREQ;
+				omap_writel(otg_ctrl | OTG_A_BUSREQ, OTG_CTRL);
 			}
 
 			if (isp->otg.host) {
@@ -818,7 +831,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp)
 			}
 		}
 
-		OTG_IRQ_SRC_REG = DRIVER_SWITCH;
+		omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
 		ret = IRQ_HANDLED;
 
 		if (kick)
@@ -834,12 +847,15 @@ static struct platform_device *otg_dev;
 
 static int otg_init(struct isp1301 *isp)
 {
+	u32 l;
+
 	if (!otg_dev)
 		return -ENODEV;
 
 	dump_regs(isp, __func__);
 	/* some of these values are board-specific... */
-	OTG_SYSCON_2_REG |= OTG_EN
+	l = omap_readl(OTG_SYSCON_2);
+	l |= OTG_EN
 		/* for B-device: */
 		| SRP_GPDATA		/* 9msec Bdev D+ pulse */
 		| SRP_GPDVBUS		/* discharge after VBUS pulse */
@@ -849,18 +865,22 @@ static int otg_init(struct isp1301 *isp)
 		| SRP_DPW		/* detect 167+ns SRP pulses */
 		| SRP_DATA | SRP_VBUS	/* accept both kinds of SRP pulse */
 		;
+	omap_writel(l, OTG_SYSCON_2);
 
 	update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
 	update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
 
 	check_state(isp, __func__);
 	pr_debug("otg: %s, %s %06x\n",
-			state_name(isp), __func__, OTG_CTRL_REG);
+			state_name(isp), __func__, omap_readl(OTG_CTRL));
 
-	OTG_IRQ_EN_REG = DRIVER_SWITCH | OPRT_CHG
+	omap_writew(DRIVER_SWITCH | OPRT_CHG
 			| B_SRP_TMROUT | B_HNP_FAIL
-			| A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT;
-	OTG_SYSCON_2_REG |= OTG_EN;
+			| A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT, OTG_IRQ_EN);
+
+	l = omap_readl(OTG_SYSCON_2);
+	l |= OTG_EN;
+	omap_writel(l, OTG_SYSCON_2);
 
 	return 0;
 }
@@ -927,7 +947,11 @@ static void otg_unbind(struct isp1301 *isp)
 
 static void b_peripheral(struct isp1301 *isp)
 {
-	OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+	u32 l;
+
+	l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+	omap_writel(l, OTG_CTRL);
+
 	usb_gadget_vbus_connect(isp->otg.gadget);
 
 #ifdef	CONFIG_USB_OTG
@@ -999,6 +1023,8 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat)
 			isp_bstat = 0;
 		}
 	} else {
+		u32 l;
+
 		/* if user unplugged mini-A end of cable,
 		 * don't bypass A_WAIT_VFALL.
 		 */
@@ -1019,8 +1045,9 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat)
 				isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1,
 						MC1_BDIS_ACON_EN);
 				isp->otg.state = OTG_STATE_B_IDLE;
-				OTG_CTRL_REG &= OTG_CTRL_REG & OTG_CTRL_MASK
-						& ~OTG_CTRL_BITS;
+				l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+				l &= ~OTG_CTRL_BITS;
+				omap_writel(l, OTG_CTRL);
 				break;
 			case OTG_STATE_B_IDLE:
 				break;
@@ -1046,7 +1073,8 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat)
 			/* FALLTHROUGH */
 		case OTG_STATE_B_SRP_INIT:
 			b_idle(isp, __func__);
-			OTG_CTRL_REG &= OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
+			l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+			omap_writel(l, OTG_CTRL);
 			/* FALLTHROUGH */
 		case OTG_STATE_B_IDLE:
 			if (isp->otg.gadget && (isp_bstat & OTG_B_SESS_VLD)) {
@@ -1130,11 +1158,11 @@ isp1301_work(struct work_struct *work)
 			case OTG_STATE_A_WAIT_VRISE:
 				isp->otg.state = OTG_STATE_A_HOST;
 				pr_debug("  --> a_host\n");
-				otg_ctrl = OTG_CTRL_REG;
+				otg_ctrl = omap_readl(OTG_CTRL);
 				otg_ctrl |= OTG_A_BUSREQ;
 				otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ)
 						& OTG_CTRL_MASK;
-				OTG_CTRL_REG = otg_ctrl;
+				omap_writel(otg_ctrl, OTG_CTRL);
 				break;
 			case OTG_STATE_B_WAIT_ACON:
 				isp->otg.state = OTG_STATE_B_HOST;
@@ -1274,7 +1302,7 @@ isp1301_set_host(struct otg_transceiver *otg, struct usb_bus *host)
 		return -ENODEV;
 
 	if (!host) {
-		OTG_IRQ_EN_REG = 0;
+		omap_writew(0, OTG_IRQ_EN);
 		power_down(isp);
 		isp->otg.host = 0;
 		return 0;
@@ -1325,12 +1353,13 @@ static int
 isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
 {
 	struct isp1301	*isp = container_of(otg, struct isp1301, otg);
+	u32 l;
 
 	if (!otg || isp != the_transceiver)
 		return -ENODEV;
 
 	if (!gadget) {
-		OTG_IRQ_EN_REG = 0;
+		omap_writew(0, OTG_IRQ_EN);
 		if (!isp->otg.default_a)
 			enable_vbus_draw(isp, 0);
 		usb_gadget_vbus_disconnect(isp->otg.gadget);
@@ -1351,9 +1380,11 @@ isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
 	isp->otg.gadget = gadget;
 	// FIXME update its refcount
 
-	OTG_CTRL_REG = (OTG_CTRL_REG & OTG_CTRL_MASK
-				& ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS))
-			| OTG_ID;
+	l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+	l &= ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS);
+	l |= OTG_ID;
+	omap_writel(l, OTG_CTRL);
+
 	power_up(isp);
 	isp->otg.state = OTG_STATE_B_IDLE;
 
@@ -1405,16 +1436,17 @@ isp1301_start_srp(struct otg_transceiver *dev)
 			|| isp->otg.state != OTG_STATE_B_IDLE)
 		return -ENODEV;
 
-	otg_ctrl = OTG_CTRL_REG;
+	otg_ctrl = omap_readl(OTG_CTRL);
 	if (!(otg_ctrl & OTG_BSESSEND))
 		return -EINVAL;
 
 	otg_ctrl |= OTG_B_BUSREQ;
 	otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK;
-	OTG_CTRL_REG = otg_ctrl;
+	omap_writel(otg_ctrl, OTG_CTRL);
 	isp->otg.state = OTG_STATE_B_SRP_INIT;
 
-	pr_debug("otg: SRP, %s ... %06x\n", state_name(isp), OTG_CTRL_REG);
+	pr_debug("otg: SRP, %s ... %06x\n", state_name(isp),
+			omap_readl(OTG_CTRL));
 #ifdef	CONFIG_USB_OTG
 	check_state(isp, __func__);
 #endif
@@ -1426,6 +1458,7 @@ isp1301_start_hnp(struct otg_transceiver *dev)
 {
 #ifdef	CONFIG_USB_OTG
 	struct isp1301	*isp = container_of(dev, struct isp1301, otg);
+	u32 l;
 
 	if (!dev || isp != the_transceiver)
 		return -ENODEV;
@@ -1452,7 +1485,9 @@ isp1301_start_hnp(struct otg_transceiver *dev)
 #endif
 		/* caller must suspend then clear A_BUSREQ */
 		usb_gadget_vbus_connect(isp->otg.gadget);
-		OTG_CTRL_REG |= OTG_A_SETB_HNPEN;
+		l = omap_readl(OTG_CTRL);
+		l |= OTG_A_SETB_HNPEN;
+		omap_writel(l, OTG_CTRL);
 
 		break;
 	case OTG_STATE_A_PERIPHERAL:
@@ -1462,7 +1497,7 @@ isp1301_start_hnp(struct otg_transceiver *dev)
 		return -EILSEQ;
 	}
 	pr_debug("otg: HNP %s, %06x ...\n",
-		state_name(isp), OTG_CTRL_REG);
+		state_name(isp), omap_readl(OTG_CTRL));
 	check_state(isp, __func__);
 	return 0;
 #else

drivers/usb/gadget/omap_udc.h

@@ -8,23 +8,22 @@
 /*
  * USB device/endpoint management registers
  */
-#define UDC_REG(offset)              __REG16(UDC_BASE + (offset))
 
-#define	UDC_REV_REG			UDC_REG(0x0)	/* Revision */
-#define	UDC_EP_NUM_REG			UDC_REG(0x4)	/* Which endpoint */
+#define	UDC_REV				(UDC_BASE + 0x0)	/* Revision */
+#define	UDC_EP_NUM			(UDC_BASE + 0x4)	/* Which endpoint */
 #	define	UDC_SETUP_SEL		(1 << 6)
 #	define	UDC_EP_SEL		(1 << 5)
 #	define	UDC_EP_DIR		(1 << 4)
 	/* low 4 bits for endpoint number */
-#define	UDC_DATA_REG			UDC_REG(0x08)	/* Endpoint FIFO */
-#define	UDC_CTRL_REG			UDC_REG(0x0C)	/* Endpoint control */
+#define	UDC_DATA			(UDC_BASE + 0x08)	/* Endpoint FIFO */
+#define	UDC_CTRL			(UDC_BASE + 0x0C)	/* Endpoint control */
 #	define	UDC_CLR_HALT		(1 << 7)
 #	define	UDC_SET_HALT		(1 << 6)
 #	define	UDC_CLRDATA_TOGGLE	(1 << 3)
 #	define	UDC_SET_FIFO_EN		(1 << 2)
 #	define	UDC_CLR_EP		(1 << 1)
 #	define	UDC_RESET_EP		(1 << 0)
-#define	UDC_STAT_FLG_REG		UDC_REG(0x10)	/* Endpoint status */
+#define	UDC_STAT_FLG			(UDC_BASE + 0x10)	/* Endpoint status */
 #	define	UDC_NO_RXPACKET		(1 << 15)
 #	define	UDC_MISS_IN		(1 << 14)
 #	define	UDC_DATA_FLUSH		(1 << 13)
@@ -38,8 +37,8 @@
 #	define	UDC_FIFO_EN		(1 << 2)
 #	define	UDC_NON_ISO_FIFO_EMPTY	(1 << 1)
 #	define	UDC_NON_ISO_FIFO_FULL	(1 << 0)
-#define	UDC_RXFSTAT_REG			UDC_REG(0x14)	/* OUT bytecount */
-#define	UDC_SYSCON1_REG			UDC_REG(0x18)	/* System config 1 */
+#define	UDC_RXFSTAT			(UDC_BASE + 0x14)	/* OUT bytecount */
+#define	UDC_SYSCON1			(UDC_BASE + 0x18)	/* System config 1 */
 #	define	UDC_CFG_LOCK		(1 << 8)
 #	define	UDC_DATA_ENDIAN		(1 << 7)
 #	define	UDC_DMA_ENDIAN		(1 << 6)
@@ -48,12 +47,12 @@
 #	define	UDC_SELF_PWR		(1 << 2)
 #	define	UDC_SOFF_DIS		(1 << 1)
 #	define	UDC_PULLUP_EN		(1 << 0)
-#define	UDC_SYSCON2_REG			UDC_REG(0x1C)	/* System config 2 */
+#define	UDC_SYSCON2			(UDC_BASE + 0x1C)	/* System config 2 */
 #	define	UDC_RMT_WKP		(1 << 6)
 #	define	UDC_STALL_CMD		(1 << 5)
 #	define	UDC_DEV_CFG		(1 << 3)
 #	define	UDC_CLR_CFG		(1 << 2)
-#define	UDC_DEVSTAT_REG			UDC_REG(0x20)	/* Device status */
+#define	UDC_DEVSTAT			(UDC_BASE + 0x20)	/* Device status */
 #	define	UDC_B_HNP_ENABLE	(1 << 9)
 #	define	UDC_A_HNP_SUPPORT	(1 << 8)
 #	define	UDC_A_ALT_HNP_SUPPORT	(1 << 7)
@@ -64,26 +63,26 @@
 #	define	UDC_ADD			(1 << 2)
 #	define	UDC_DEF			(1 << 1)
 #	define	UDC_ATT			(1 << 0)
-#define	UDC_SOF_REG			UDC_REG(0x24)	/* Start of frame */
+#define	UDC_SOF				(UDC_BASE + 0x24)	/* Start of frame */
 #	define	UDC_FT_LOCK		(1 << 12)
 #	define	UDC_TS_OK		(1 << 11)
 #	define	UDC_TS			0x03ff
-#define	UDC_IRQ_EN_REG			UDC_REG(0x28)	/* Interrupt enable */
+#define	UDC_IRQ_EN			(UDC_BASE + 0x28)	/* Interrupt enable */
 #	define	UDC_SOF_IE		(1 << 7)
 #	define	UDC_EPN_RX_IE		(1 << 5)
 #	define	UDC_EPN_TX_IE		(1 << 4)
 #	define	UDC_DS_CHG_IE		(1 << 3)
 #	define	UDC_EP0_IE		(1 << 0)
-#define	UDC_DMA_IRQ_EN_REG		UDC_REG(0x2C)	/* DMA irq enable */
+#define	UDC_DMA_IRQ_EN			(UDC_BASE + 0x2C)	/* DMA irq enable */
 	/* rx/tx dma channels numbered 1-3 not 0-2 */
 #	define	UDC_TX_DONE_IE(n)	(1 << (4 * (n) - 2))
 #	define	UDC_RX_CNT_IE(n)	(1 << (4 * (n) - 3))
 #	define	UDC_RX_EOT_IE(n)	(1 << (4 * (n) - 4))
-#define	UDC_IRQ_SRC_REG			UDC_REG(0x30)	/* Interrupt source */
+#define	UDC_IRQ_SRC			(UDC_BASE + 0x30)	/* Interrupt source */
 #	define	UDC_TXN_DONE		(1 << 10)
 #	define	UDC_RXN_CNT		(1 << 9)
 #	define	UDC_RXN_EOT		(1 << 8)
-#	define	UDC_SOF			(1 << 7)
+#	define	UDC_IRQ_SOF		(1 << 7)
 #	define	UDC_EPN_RX		(1 << 5)
 #	define	UDC_EPN_TX		(1 << 4)
 #	define	UDC_DS_CHG		(1 << 3)
@@ -91,41 +90,41 @@
 #	define	UDC_EP0_RX		(1 << 1)
 #	define	UDC_EP0_TX		(1 << 0)
 #	define	UDC_IRQ_SRC_MASK	0x7bf
-#define	UDC_EPN_STAT_REG		UDC_REG(0x34)	/* EP irq status */
-#define	UDC_DMAN_STAT_REG		UDC_REG(0x38)	/* DMA irq status */
+#define	UDC_EPN_STAT			(UDC_BASE + 0x34)	/* EP irq status */
+#define	UDC_DMAN_STAT			(UDC_BASE + 0x38)	/* DMA irq status */
 #	define	UDC_DMA_RX_SB		(1 << 12)
 #	define	UDC_DMA_RX_SRC(x)	(((x)>>8) & 0xf)
 #	define	UDC_DMA_TX_SRC(x)	(((x)>>0) & 0xf)
 
 
 /* DMA configuration registers:  up to three channels in each direction.  */
-#define	UDC_RXDMA_CFG_REG		UDC_REG(0x40)	/* 3 eps for RX DMA */
+#define	UDC_RXDMA_CFG			(UDC_BASE + 0x40)	/* 3 eps for RX DMA */
 #	define	UDC_DMA_REQ		(1 << 12)
-#define	UDC_TXDMA_CFG_REG		UDC_REG(0x44)	/* 3 eps for TX DMA */
-#define	UDC_DATA_DMA_REG		UDC_REG(0x48)	/* rx/tx fifo addr */
+#define	UDC_TXDMA_CFG			(UDC_BASE + 0x44)	/* 3 eps for TX DMA */
+#define	UDC_DATA_DMA			(UDC_BASE + 0x48)	/* rx/tx fifo addr */
 
 /* rx/tx dma control, numbering channels 1-3 not 0-2 */
-#define	UDC_TXDMA_REG(chan)		UDC_REG(0x50 - 4 + 4 * (chan))
+#define	UDC_TXDMA(chan)			(UDC_BASE + 0x50 - 4 + 4 * (chan))
 #	define UDC_TXN_EOT		(1 << 15)	/* bytes vs packets */
 #	define UDC_TXN_START		(1 << 14)	/* start transfer */
 #	define UDC_TXN_TSC		0x03ff		/* units in xfer */
-#define	UDC_RXDMA_REG(chan)		UDC_REG(0x60 - 4 + 4 * (chan))
+#define	UDC_RXDMA(chan)			(UDC_BASE + 0x60 - 4 + 4 * (chan))
 #	define UDC_RXN_STOP		(1 << 15)	/* enable EOT irq */
 #	define UDC_RXN_TC		0x00ff		/* packets in xfer */
 
 
 /*
  * Endpoint configuration registers (used before CFG_LOCK is set)
- * UDC_EP_TX_REG(0) is unused
+ * UDC_EP_TX(0) is unused
  */
-#define	UDC_EP_RX_REG(endpoint)		UDC_REG(0x80 + (endpoint)*4)
+#define	UDC_EP_RX(endpoint)		(UDC_BASE + 0x80 + (endpoint)*4)
 #	define	UDC_EPN_RX_VALID	(1 << 15)
 #	define	UDC_EPN_RX_DB		(1 << 14)
 	/* buffer size in bits 13, 12 */
 #	define	UDC_EPN_RX_ISO		(1 << 11)
 	/* buffer pointer in low 11 bits */
-#define	UDC_EP_TX_REG(endpoint)		UDC_REG(0xc0 + (endpoint)*4)
-	/* same bitfields as in RX_REG */
+#define	UDC_EP_TX(endpoint)		(UDC_BASE + 0xc0 + (endpoint)*4)
+	/* same bitfields as in RX */
 
 /*-------------------------------------------------------------------------*/
 
@@ -195,14 +194,14 @@ struct omap_udc {
 
 /*-------------------------------------------------------------------------*/
 
-#define	MOD_CONF_CTRL_0_REG	__REG32(MOD_CONF_CTRL_0)
-#define	VBUS_W2FC_1510		(1 << 17)	/* 0 gpio0, 1 dvdd2 pin */
+/* MOD_CONF_CTRL_0 */
+#define VBUS_W2FC_1510		(1 << 17)	/* 0 gpio0, 1 dvdd2 pin */
 
-#define	FUNC_MUX_CTRL_0_REG	__REG32(FUNC_MUX_CTRL_0)
+/* FUNC_MUX_CTRL_0 */
 #define	VBUS_CTRL_1510		(1 << 19)	/* 1 connected (software) */
 #define	VBUS_MODE_1510		(1 << 18)	/* 0 hardware, 1 software */
 
-#define	HMC_1510	((MOD_CONF_CTRL_0_REG >> 1) & 0x3f)
-#define	HMC_1610	(OTG_SYSCON_2_REG & 0x3f)
+#define	HMC_1510	((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f)
+#define	HMC_1610	(omap_readl(OTG_SYSCON_2) & 0x3f)
 #define	HMC		(cpu_is_omap15xx() ? HMC_1510 : HMC_1610)
 

drivers/usb/host/ohci-omap.c

@@ -169,13 +169,16 @@ static void start_hnp(struct ohci_hcd *ohci)
 {
 	const unsigned	port = ohci_to_hcd(ohci)->self.otg_port - 1;
 	unsigned long	flags;
+	u32 l;
 
 	otg_start_hnp(ohci->transceiver);
 
 	local_irq_save(flags);
 	ohci->transceiver->state = OTG_STATE_A_SUSPEND;
 	writel (RH_PS_PSS, &ohci->regs->roothub.portstatus [port]);
-	OTG_CTRL_REG &= ~OTG_A_BUSREQ;
+	l = omap_readl(OTG_CTRL);
+	l &= ~OTG_A_BUSREQ;
+	omap_writel(l, OTG_CTRL);
 	local_irq_restore(flags);
 }
 

include/asm-arm/arch-omap/usb.h

@@ -34,11 +34,8 @@
 /*
  * OTG and transceiver registers, for OMAPs starting with ARM926
  */
-#define OTG_REG32(offset)		__REG32(OTG_BASE + (offset))
-#define OTG_REG16(offset)		__REG16(OTG_BASE + (offset))
-
-#define OTG_REV_REG			OTG_REG32(0x00)
-#define OTG_SYSCON_1_REG		OTG_REG32(0x04)
+#define OTG_REV				(OTG_BASE + 0x00)
+#define OTG_SYSCON_1			(OTG_BASE + 0x04)
 #	define	 USB2_TRX_MODE(w)	(((w)>>24)&0x07)
 #	define	 USB1_TRX_MODE(w)	(((w)>>20)&0x07)
 #	define	 USB0_TRX_MODE(w)	(((w)>>16)&0x07)
@@ -47,7 +44,7 @@
 #	define	 DEV_IDLE_EN		(1 << 13)
 #	define	 OTG_RESET_DONE		(1 << 2)
 #	define	 OTG_SOFT_RESET		(1 << 1)
-#define OTG_SYSCON_2_REG		OTG_REG32(0x08)
+#define OTG_SYSCON_2			(OTG_BASE + 0x08)
 #	define	 OTG_EN			(1 << 31)
 #	define	 USBX_SYNCHRO		(1 << 30)
 #	define	 OTG_MST16		(1 << 29)
@@ -65,7 +62,7 @@
 #	define	 HMC_TLLSPEED		(1 << 7)
 #	define	 HMC_TLLATTACH		(1 << 6)
 #	define	 OTG_HMC(w)		(((w)>>0)&0x3f)
-#define OTG_CTRL_REG			OTG_REG32(0x0c)
+#define OTG_CTRL			(OTG_BASE + 0x0c)
 #	define	 OTG_USB2_EN		(1 << 29)
 #	define	 OTG_USB2_DP		(1 << 28)
 #	define	 OTG_USB2_DM		(1 << 27)
@@ -92,7 +89,7 @@
 #	define	 OTG_PD_VBUS		(1 << 2)
 #	define	 OTG_PU_VBUS		(1 << 1)
 #	define	 OTG_PU_ID		(1 << 0)
-#define OTG_IRQ_EN_REG			OTG_REG16(0x10)
+#define OTG_IRQ_EN			(OTG_BASE + 0x10)	/* 16-bit */
 #	define	 DRIVER_SWITCH		(1 << 15)
 #	define	 A_VBUS_ERR		(1 << 13)
 #	define	 A_REQ_TMROUT		(1 << 12)
@@ -102,9 +99,9 @@
 #	define	 B_SRP_DONE		(1 << 8)
 #	define	 B_SRP_STARTED		(1 << 7)
 #	define	 OPRT_CHG		(1 << 0)
-#define OTG_IRQ_SRC_REG			OTG_REG16(0x14)
+#define OTG_IRQ_SRC			(OTG_BASE + 0x14)	/* 16-bit */
 	// same bits as in IRQ_EN
-#define OTG_OUTCTRL_REG			OTG_REG16(0x18)
+#define OTG_OUTCTRL			(OTG_BASE + 0x18)	/* 16-bit */
 #	define	 OTGVPD			(1 << 14)
 #	define	 OTGVPU			(1 << 13)
 #	define	 OTGPUID		(1 << 12)
@@ -117,13 +114,13 @@
 #	define	 USB0VDR		(1 << 2)
 #	define	 USB0PDEN		(1 << 1)
 #	define	 USB0PUEN		(1 << 0)
-#define OTG_TEST_REG			OTG_REG16(0x20)
-#define OTG_VENDOR_CODE_REG		OTG_REG32(0xfc)
+#define OTG_TEST			(OTG_BASE + 0x20)	/* 16-bit */
+#define OTG_VENDOR_CODE			(OTG_BASE + 0xfc)	/* 16-bit */
 
 /*-------------------------------------------------------------------------*/
 
 /* OMAP1 */
-#define	USB_TRANSCEIVER_CTRL_REG	__REG32(0xfffe1000 + 0x0064)
+#define	USB_TRANSCEIVER_CTRL		(0xfffe1000 + 0x0064)
 #	define	CONF_USB2_UNI_R		(1 << 8)
 #	define	CONF_USB1_UNI_R		(1 << 7)
 #	define	CONF_USB_PORT0_R(x)	(((x)>>4)&0x7)