提交 e884fc64 编写于 作者: A Alex Deucher

drm/radeon: disable the crtcs in mc_stop (r5xx-r7xx) (v2)

Just disabling the mem requests should be enough, but
that doesn't seem to work correctly on efi systems.

v2: blank displays first, then disable.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
上级 968c0166
...@@ -360,6 +360,7 @@ ...@@ -360,6 +360,7 @@
#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0 #define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0
#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 #define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
#define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8
/* master controls */ /* master controls */
#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 #define AVIVO_DC_CRTC_MASTER_EN 0x60f8
......
...@@ -303,8 +303,10 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) ...@@ -303,8 +303,10 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
radeon_wait_for_vblank(rdev, i); radeon_wait_for_vblank(rdev, i);
WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
} }
/* wait for the next frame */ /* wait for the next frame */
frame_count = radeon_get_vblank_counter(rdev, i); frame_count = radeon_get_vblank_counter(rdev, i);
...@@ -313,6 +315,15 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) ...@@ -313,6 +315,15 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
break; break;
udelay(1); udelay(1);
} }
/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
tmp &= ~AVIVO_CRTC_EN;
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
save->crtc_enabled[i] = false;
/* ***** */
} else { } else {
save->crtc_enabled[i] = false; save->crtc_enabled[i] = false;
} }
......
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