提交 e5d03ac2 编写于 作者: R Rex Zhu 提交者: Alex Deucher

drm/amd/powerplay: Unify dpm level defines

Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 db7da7aa
...@@ -241,13 +241,6 @@ enum amdgpu_pcie_gen { ...@@ -241,13 +241,6 @@ enum amdgpu_pcie_gen {
AMDGPU_PCIE_GEN_INVALID = 0xffff AMDGPU_PCIE_GEN_INVALID = 0xffff
}; };
enum amdgpu_dpm_forced_level {
AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
};
struct amdgpu_dpm_funcs { struct amdgpu_dpm_funcs {
int (*get_temperature)(struct amdgpu_device *adev); int (*get_temperature)(struct amdgpu_device *adev);
int (*pre_set_power_state)(struct amdgpu_device *adev); int (*pre_set_power_state)(struct amdgpu_device *adev);
...@@ -258,7 +251,7 @@ struct amdgpu_dpm_funcs { ...@@ -258,7 +251,7 @@ struct amdgpu_dpm_funcs {
u32 (*get_mclk)(struct amdgpu_device *adev, bool low); u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); int (*force_performance_level)(struct amdgpu_device *adev, enum amd_dpm_forced_level level);
bool (*vblank_too_short)(struct amdgpu_device *adev); bool (*vblank_too_short)(struct amdgpu_device *adev);
void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
void (*powergate_vce)(struct amdgpu_device *adev, bool gate); void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
...@@ -353,9 +346,6 @@ struct amdgpu_dpm_funcs { ...@@ -353,9 +346,6 @@ struct amdgpu_dpm_funcs {
#define amdgpu_dpm_get_current_power_state(adev) \ #define amdgpu_dpm_get_current_power_state(adev) \
(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
#define amdgpu_dpm_get_performance_level(adev) \
(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
#define amdgpu_dpm_get_pp_num_states(adev, data) \ #define amdgpu_dpm_get_pp_num_states(adev, data) \
(adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
...@@ -393,6 +383,11 @@ struct amdgpu_dpm_funcs { ...@@ -393,6 +383,11 @@ struct amdgpu_dpm_funcs {
(adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \ (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \
(adev)->pm.funcs->get_vce_clock_state((adev), (i))) (adev)->pm.funcs->get_vce_clock_state((adev), (i)))
#define amdgpu_dpm_get_performance_level(adev) \
((adev)->pp_enabled ? \
(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) : \
(adev)->pm.dpm.forced_level)
struct amdgpu_dpm { struct amdgpu_dpm {
struct amdgpu_ps *ps; struct amdgpu_ps *ps;
/* number of valid power states */ /* number of valid power states */
...@@ -440,7 +435,7 @@ struct amdgpu_dpm { ...@@ -440,7 +435,7 @@ struct amdgpu_dpm {
/* thermal handling */ /* thermal handling */
struct amdgpu_dpm_thermal thermal; struct amdgpu_dpm_thermal thermal;
/* forced levels */ /* forced levels */
enum amdgpu_dpm_forced_level forced_level; enum amd_dpm_forced_level forced_level;
}; };
struct amdgpu_pm { struct amdgpu_pm {
......
...@@ -112,28 +112,19 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev, ...@@ -112,28 +112,19 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
{ {
struct drm_device *ddev = dev_get_drvdata(dev); struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private; struct amdgpu_device *adev = ddev->dev_private;
enum amd_dpm_forced_level level;
if ((adev->flags & AMD_IS_PX) && if ((adev->flags & AMD_IS_PX) &&
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return snprintf(buf, PAGE_SIZE, "off\n"); return snprintf(buf, PAGE_SIZE, "off\n");
if (adev->pp_enabled) { level = amdgpu_dpm_get_performance_level(adev);
enum amd_dpm_forced_level level; return snprintf(buf, PAGE_SIZE, "%s\n",
(level & (AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
level = amdgpu_dpm_get_performance_level(adev); (level & AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
return snprintf(buf, PAGE_SIZE, "%s\n", (level & AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
(level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : (level & AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
(level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : "unknown"));
(level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
(level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : "unknown");
} else {
enum amdgpu_dpm_forced_level level;
level = adev->pm.dpm.forced_level;
return snprintf(buf, PAGE_SIZE, "%s\n",
(level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
(level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
}
} }
static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
...@@ -143,7 +134,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, ...@@ -143,7 +134,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
{ {
struct drm_device *ddev = dev_get_drvdata(dev); struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private; struct amdgpu_device *adev = ddev->dev_private;
enum amdgpu_dpm_forced_level level; enum amd_dpm_forced_level level;
int ret = 0; int ret = 0;
/* Can't force performance level when the card is off */ /* Can't force performance level when the card is off */
...@@ -152,13 +143,13 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, ...@@ -152,13 +143,13 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
return -EINVAL; return -EINVAL;
if (strncmp("low", buf, strlen("low")) == 0) { if (strncmp("low", buf, strlen("low")) == 0) {
level = AMDGPU_DPM_FORCED_LEVEL_LOW; level = AMD_DPM_FORCED_LEVEL_LOW;
} else if (strncmp("high", buf, strlen("high")) == 0) { } else if (strncmp("high", buf, strlen("high")) == 0) {
level = AMDGPU_DPM_FORCED_LEVEL_HIGH; level = AMD_DPM_FORCED_LEVEL_HIGH;
} else if (strncmp("auto", buf, strlen("auto")) == 0) { } else if (strncmp("auto", buf, strlen("auto")) == 0) {
level = AMDGPU_DPM_FORCED_LEVEL_AUTO; level = AMD_DPM_FORCED_LEVEL_AUTO;
} else if (strncmp("manual", buf, strlen("manual")) == 0) { } else if (strncmp("manual", buf, strlen("manual")) == 0) {
level = AMDGPU_DPM_FORCED_LEVEL_MANUAL; level = AMD_DPM_FORCED_LEVEL_MANUAL;
} else { } else {
count = -EINVAL; count = -EINVAL;
goto fail; goto fail;
...@@ -1060,9 +1051,9 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) ...@@ -1060,9 +1051,9 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
if (adev->pm.funcs->force_performance_level) { if (adev->pm.funcs->force_performance_level) {
if (adev->pm.dpm.thermal_active) { if (adev->pm.dpm.thermal_active) {
enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level; enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
/* force low perf level for thermal */ /* force low perf level for thermal */
amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW); amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
/* save the user's level */ /* save the user's level */
adev->pm.dpm.forced_level = level; adev->pm.dpm.forced_level = level;
} else { } else {
......
...@@ -4336,13 +4336,13 @@ static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev, ...@@ -4336,13 +4336,13 @@ static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
static int ci_dpm_force_performance_level(struct amdgpu_device *adev, static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
enum amdgpu_dpm_forced_level level) enum amd_dpm_forced_level level)
{ {
struct ci_power_info *pi = ci_get_pi(adev); struct ci_power_info *pi = ci_get_pi(adev);
u32 tmp, levels, i; u32 tmp, levels, i;
int ret; int ret;
if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) { if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
if ((!pi->pcie_dpm_key_disabled) && if ((!pi->pcie_dpm_key_disabled) &&
pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
levels = 0; levels = 0;
...@@ -4403,7 +4403,7 @@ static int ci_dpm_force_performance_level(struct amdgpu_device *adev, ...@@ -4403,7 +4403,7 @@ static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
} }
} }
} }
} else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) { } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
if ((!pi->sclk_dpm_key_disabled) && if ((!pi->sclk_dpm_key_disabled) &&
pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
levels = ci_get_lowest_enabled_level(adev, levels = ci_get_lowest_enabled_level(adev,
...@@ -4452,7 +4452,7 @@ static int ci_dpm_force_performance_level(struct amdgpu_device *adev, ...@@ -4452,7 +4452,7 @@ static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
udelay(1); udelay(1);
} }
} }
} else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) { } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
if (!pi->pcie_dpm_key_disabled) { if (!pi->pcie_dpm_key_disabled) {
PPSMC_Result smc_result; PPSMC_Result smc_result;
...@@ -6262,7 +6262,7 @@ static int ci_dpm_sw_init(void *handle) ...@@ -6262,7 +6262,7 @@ static int ci_dpm_sw_init(void *handle)
/* default to balanced state */ /* default to balanced state */
adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
adev->pm.default_sclk = adev->clock.default_sclk; adev->pm.default_sclk = adev->clock.default_sclk;
adev->pm.default_mclk = adev->clock.default_mclk; adev->pm.default_mclk = adev->clock.default_mclk;
adev->pm.current_sclk = adev->clock.default_sclk; adev->pm.current_sclk = adev->clock.default_sclk;
...@@ -6572,7 +6572,7 @@ static int ci_dpm_force_clock_level(struct amdgpu_device *adev, ...@@ -6572,7 +6572,7 @@ static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
struct ci_power_info *pi = ci_get_pi(adev); struct ci_power_info *pi = ci_get_pi(adev);
if (adev->pm.dpm.forced_level if (adev->pm.dpm.forced_level
!= AMDGPU_DPM_FORCED_LEVEL_MANUAL) != AMD_DPM_FORCED_LEVEL_MANUAL)
return -EINVAL; return -EINVAL;
switch (type) { switch (type) {
......
...@@ -1904,19 +1904,19 @@ static int kv_enable_nb_dpm(struct amdgpu_device *adev, ...@@ -1904,19 +1904,19 @@ static int kv_enable_nb_dpm(struct amdgpu_device *adev,
} }
static int kv_dpm_force_performance_level(struct amdgpu_device *adev, static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
enum amdgpu_dpm_forced_level level) enum amd_dpm_forced_level level)
{ {
int ret; int ret;
if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) { if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
ret = kv_force_dpm_highest(adev); ret = kv_force_dpm_highest(adev);
if (ret) if (ret)
return ret; return ret;
} else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) { } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
ret = kv_force_dpm_lowest(adev); ret = kv_force_dpm_lowest(adev);
if (ret) if (ret)
return ret; return ret;
} else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) { } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
ret = kv_unforce_levels(adev); ret = kv_unforce_levels(adev);
if (ret) if (ret)
return ret; return ret;
...@@ -3029,7 +3029,7 @@ static int kv_dpm_sw_init(void *handle) ...@@ -3029,7 +3029,7 @@ static int kv_dpm_sw_init(void *handle)
/* default to balanced state */ /* default to balanced state */
adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
adev->pm.default_sclk = adev->clock.default_sclk; adev->pm.default_sclk = adev->clock.default_sclk;
adev->pm.default_mclk = adev->clock.default_mclk; adev->pm.default_mclk = adev->clock.default_mclk;
adev->pm.current_sclk = adev->clock.default_sclk; adev->pm.current_sclk = adev->clock.default_sclk;
......
...@@ -3906,25 +3906,25 @@ static int si_restrict_performance_levels_before_switch(struct amdgpu_device *ad ...@@ -3906,25 +3906,25 @@ static int si_restrict_performance_levels_before_switch(struct amdgpu_device *ad
} }
static int si_dpm_force_performance_level(struct amdgpu_device *adev, static int si_dpm_force_performance_level(struct amdgpu_device *adev,
enum amdgpu_dpm_forced_level level) enum amd_dpm_forced_level level)
{ {
struct amdgpu_ps *rps = adev->pm.dpm.current_ps; struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
struct si_ps *ps = si_get_ps(rps); struct si_ps *ps = si_get_ps(rps);
u32 levels = ps->performance_level_count; u32 levels = ps->performance_level_count;
if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) { if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
return -EINVAL; return -EINVAL;
if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
return -EINVAL; return -EINVAL;
} else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) { } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
return -EINVAL; return -EINVAL;
if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
return -EINVAL; return -EINVAL;
} else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) { } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
return -EINVAL; return -EINVAL;
...@@ -7746,7 +7746,7 @@ static int si_dpm_sw_init(void *handle) ...@@ -7746,7 +7746,7 @@ static int si_dpm_sw_init(void *handle)
/* default to balanced state */ /* default to balanced state */
adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
adev->pm.default_sclk = adev->clock.default_sclk; adev->pm.default_sclk = adev->clock.default_sclk;
adev->pm.default_mclk = adev->clock.default_mclk; adev->pm.default_mclk = adev->clock.default_mclk;
adev->pm.current_sclk = adev->clock.default_sclk; adev->pm.current_sclk = adev->clock.default_sclk;
......
...@@ -80,6 +80,13 @@ enum amd_clockgating_state { ...@@ -80,6 +80,13 @@ enum amd_clockgating_state {
AMD_CG_STATE_UNGATE, AMD_CG_STATE_UNGATE,
}; };
enum amd_dpm_forced_level {
AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
AMD_DPM_FORCED_LEVEL_LOW = 0x4,
AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
};
enum amd_powergating_state { enum amd_powergating_state {
AMD_PG_STATE_GATE = 0, AMD_PG_STATE_GATE = 0,
AMD_PG_STATE_UNGATE, AMD_PG_STATE_UNGATE,
......
...@@ -135,13 +135,6 @@ enum amd_pp_event { ...@@ -135,13 +135,6 @@ enum amd_pp_event {
AMD_PP_EVENT_MAX AMD_PP_EVENT_MAX
}; };
enum amd_dpm_forced_level {
AMD_DPM_FORCED_LEVEL_AUTO = 0,
AMD_DPM_FORCED_LEVEL_LOW = 1,
AMD_DPM_FORCED_LEVEL_HIGH = 2,
AMD_DPM_FORCED_LEVEL_MANUAL = 3,
};
struct amd_pp_init { struct amd_pp_init {
struct cgs_device *device; struct cgs_device *device;
uint32_t chip_family; uint32_t chip_family;
......
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