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提交 e3e1970f 编写于 作者: T Tony Lindgren
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Merge tag 'for-v3.12/dra7xx' of... 

Merge tag 'for-v3.12/dra7xx' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.12/soc

This series adds basic TI DRA7xx PRCM and hwmod support.

Basic test logs are available here:

http://www.pwsan.com/omap/testlogs/dra7xx_prcm_devel_v3.12/20130823050445/

Note that DRA7xx could not be tested locally, since I don't have a board.
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arch/arm/mach-omap2/Makefile
浏览文件 @ e3e1970f
......@@ -63,6 +63,7 @@ obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# Pin multiplexing
obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
......@@ -148,6 +149,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
......@@ -166,6 +168,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
......@@ -209,6 +212,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
......
arch/arm/mach-omap2/board-generic.c
浏览文件 @ e3e1970f
......@@ -238,5 +238,6 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
.init_machine = omap_generic_init,
.init_time = omap5_realtime_timer_init,
.dt_compat = dra7xx_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
#endif
arch/arm/mach-omap2/clockdomain.h
浏览文件 @ e3e1970f
......@@ -217,6 +217,7 @@ extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
extern void __init dra7xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);
......
arch/arm/mach-omap2/clockdomains7xx_data.c 0 → 100644
浏览文件 @ e3e1970f
此差异已折叠。
arch/arm/mach-omap2/cm-regbits-7xx.h 0 → 100644
浏览文件 @ e3e1970f
/*
* DRA7xx Clock Management register bits
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
#define DRA7XX_ATL_STATDEP_SHIFT 30
#define DRA7XX_CAM_STATDEP_SHIFT 9
#define DRA7XX_DSP1_STATDEP_SHIFT 1
#define DRA7XX_DSP2_STATDEP_SHIFT 18
#define DRA7XX_DSS_STATDEP_SHIFT 8
#define DRA7XX_EMIF_STATDEP_SHIFT 4
#define DRA7XX_EVE1_STATDEP_SHIFT 19
#define DRA7XX_EVE2_STATDEP_SHIFT 20
#define DRA7XX_EVE3_STATDEP_SHIFT 21
#define DRA7XX_EVE4_STATDEP_SHIFT 22
#define DRA7XX_GMAC_STATDEP_SHIFT 25
#define DRA7XX_GPU_STATDEP_SHIFT 10
#define DRA7XX_IPU1_STATDEP_SHIFT 23
#define DRA7XX_IPU2_STATDEP_SHIFT 0
#define DRA7XX_IPU_STATDEP_SHIFT 24
#define DRA7XX_IVA_STATDEP_SHIFT 2
#define DRA7XX_L3INIT_STATDEP_SHIFT 7
#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5
#define DRA7XX_L4CFG_STATDEP_SHIFT 12
#define DRA7XX_L4PER2_STATDEP_SHIFT 26
#define DRA7XX_L4PER3_STATDEP_SHIFT 27
#define DRA7XX_L4PER_STATDEP_SHIFT 13
#define DRA7XX_L4SEC_STATDEP_SHIFT 14
#define DRA7XX_PCIE_STATDEP_SHIFT 29
#define DRA7XX_VPE_STATDEP_SHIFT 28
#define DRA7XX_WKUPAON_STATDEP_SHIFT 15
#endif
arch/arm/mach-omap2/cm1_7xx.h 0 → 100644
浏览文件 @ e3e1970f
/*
* DRA7xx CM1 instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
#include "cm_44xx_54xx.h"
/* CM1 base address */
#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
/* CM_CORE_AON instances */
#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
/* CM_CORE_AON clockdomain register offsets (from instance start) */
#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
/* CM_CORE_AON */
/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008
#endif
arch/arm/mach-omap2/cm2_7xx.h 0 → 100644
浏览文件 @ e3e1970f
此差异已折叠。
arch/arm/mach-omap2/io.c
浏览文件 @ e3e1970f
......@@ -665,6 +665,11 @@ void __init dra7xx_init_early(void)
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
dra7xx_powerdomains_init();
dra7xx_clockdomains_init();
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
}
#endif
......
arch/arm/mach-omap2/omap_hwmod.h
浏览文件 @ e3e1970f
......@@ -751,6 +751,7 @@ extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
extern int dra7xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
......
arch/arm/mach-omap2/omap_hwmod_7xx_data.c 0 → 100644
浏览文件 @ e3e1970f
此差异已折叠。
arch/arm/mach-omap2/powerdomain.h
浏览文件 @ e3e1970f
......@@ -256,6 +256,7 @@ extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern void omap54xx_powerdomains_init(void);
extern void dra7xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
......
arch/arm/mach-omap2/powerdomains7xx_data.c 0 → 100644
浏览文件 @ e3e1970f
/*
* DRA7xx Power domains framework
*
* Copyright (C) 2009-2013 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Nokia Corporation
*
* Generated by code originally written by:
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include "powerdomain.h"
#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm7xx.h"
#include "prcm_mpu7xx.h"
/* iva_7xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_7xx_pwrdm = {
.name = "iva_pwrdm",
.prcm_offs = DRA7XX_PRM_IVA_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 4,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* rtc_7xx_pwrdm: */
static struct powerdomain rtc_7xx_pwrdm = {
.name = "rtc_pwrdm",
.prcm_offs = DRA7XX_PRM_RTC_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
};
/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_7xx_pwrdm = {
.name = "custefuse_pwrdm",
.prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* ipu_7xx_pwrdm: Audio back end power domain */
static struct powerdomain ipu_7xx_pwrdm = {
.name = "ipu_pwrdm",
.prcm_offs = DRA7XX_PRM_IPU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* aessmem */
[1] = PWRSTS_OFF_RET, /* periphmem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* aessmem */
[1] = PWRSTS_OFF_RET, /* periphmem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dss_7xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_7xx_pwrdm = {
.name = "dss_pwrdm",
.prcm_offs = DRA7XX_PRM_DSS_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dss_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dss_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l4per_7xx_pwrdm: Target peripherals power domain */
static struct powerdomain l4per_7xx_pwrdm = {
.name = "l4per_pwrdm",
.prcm_offs = DRA7XX_PRM_L4PER_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* nonretained_bank */
[1] = PWRSTS_OFF_RET, /* retained_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* nonretained_bank */
[1] = PWRSTS_OFF_RET, /* retained_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* gpu_7xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gpu_7xx_pwrdm = {
.name = "gpu_pwrdm",
.prcm_offs = DRA7XX_PRM_GPU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* gpu_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* gpu_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* wkupaon_7xx_pwrdm: Wake-up power domain */
static struct powerdomain wkupaon_7xx_pwrdm = {
.name = "wkupaon_pwrdm",
.prcm_offs = DRA7XX_PRM_WKUPAON_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
.banks = 1,
.pwrsts_mem_ret = {
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* wkup_bank */
},
};
/* core_7xx_pwrdm: CORE power domain */
static struct powerdomain core_7xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = DRA7XX_PRM_CORE_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRSTS_OFF_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRSTS_OFF_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
static struct powerdomain coreaon_7xx_pwrdm = {
.name = "coreaon_pwrdm",
.prcm_offs = DRA7XX_PRM_COREAON_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
};
/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_7xx_pwrdm = {
.name = "cpu0_pwrdm",
.prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cpu0_l1 */
},
};
/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_7xx_pwrdm = {
.name = "cpu1_pwrdm",
.prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cpu1_l1 */
},
};
/* vpe_7xx_pwrdm: */
static struct powerdomain vpe_7xx_pwrdm = {
.name = "vpe_pwrdm",
.prcm_offs = DRA7XX_PRM_VPE_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* vpe_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* vpe_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_7xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = DRA7XX_PRM_MPU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
[1] = PWRSTS_RET, /* mpu_ram */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
[1] = PWRSTS_OFF_RET, /* mpu_ram */
},
};
/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
static struct powerdomain l3init_7xx_pwrdm = {
.name = "l3init_pwrdm",
.prcm_offs = DRA7XX_PRM_L3INIT_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* gmac_bank */
[1] = PWRSTS_OFF_RET, /* l3init_bank1 */
[2] = PWRSTS_OFF_RET, /* l3init_bank2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* gmac_bank */
[1] = PWRSTS_OFF_RET, /* l3init_bank1 */
[2] = PWRSTS_OFF_RET, /* l3init_bank2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* eve3_7xx_pwrdm: */
static struct powerdomain eve3_7xx_pwrdm = {
.name = "eve3_pwrdm",
.prcm_offs = DRA7XX_PRM_EVE3_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* eve3_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* eve3_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* emu_7xx_pwrdm: Emulation power domain */
static struct powerdomain emu_7xx_pwrdm = {
.name = "emu_pwrdm",
.prcm_offs = DRA7XX_PRM_EMU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* emu_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* emu_bank */
},
};
/* dsp2_7xx_pwrdm: */
static struct powerdomain dsp2_7xx_pwrdm = {
.name = "dsp2_pwrdm",
.prcm_offs = DRA7XX_PRM_DSP2_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dsp2_edma */
[1] = PWRSTS_OFF_RET, /* dsp2_l1 */
[2] = PWRSTS_OFF_RET, /* dsp2_l2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dsp2_edma */
[1] = PWRSTS_OFF_RET, /* dsp2_l1 */
[2] = PWRSTS_OFF_RET, /* dsp2_l2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dsp1_7xx_pwrdm: Tesla processor power domain */
static struct powerdomain dsp1_7xx_pwrdm = {
.name = "dsp1_pwrdm",
.prcm_offs = DRA7XX_PRM_DSP1_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dsp1_edma */
[1] = PWRSTS_OFF_RET, /* dsp1_l1 */
[2] = PWRSTS_OFF_RET, /* dsp1_l2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dsp1_edma */
[1] = PWRSTS_OFF_RET, /* dsp1_l1 */
[2] = PWRSTS_OFF_RET, /* dsp1_l2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cam_7xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_7xx_pwrdm = {
.name = "cam_pwrdm",
.prcm_offs = DRA7XX_PRM_CAM_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* vip_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* vip_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* eve4_7xx_pwrdm: */
static struct powerdomain eve4_7xx_pwrdm = {
.name = "eve4_pwrdm",
.prcm_offs = DRA7XX_PRM_EVE4_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* eve4_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* eve4_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* eve2_7xx_pwrdm: */
static struct powerdomain eve2_7xx_pwrdm = {
.name = "eve2_pwrdm",
.prcm_offs = DRA7XX_PRM_EVE2_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* eve2_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* eve2_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* eve1_7xx_pwrdm: */
static struct powerdomain eve1_7xx_pwrdm = {
.name = "eve1_pwrdm",
.prcm_offs = DRA7XX_PRM_EVE1_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* eve1_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* eve1_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*
* The following power domains are not under SW control
*
* mpuaon
* mmaon
*/
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_dra7xx[] __initdata = {
&iva_7xx_pwrdm,
&rtc_7xx_pwrdm,
&custefuse_7xx_pwrdm,
&ipu_7xx_pwrdm,
&dss_7xx_pwrdm,
&l4per_7xx_pwrdm,
&gpu_7xx_pwrdm,
&wkupaon_7xx_pwrdm,
&core_7xx_pwrdm,
&coreaon_7xx_pwrdm,
&cpu0_7xx_pwrdm,
&cpu1_7xx_pwrdm,
&vpe_7xx_pwrdm,
&mpu_7xx_pwrdm,
&l3init_7xx_pwrdm,
&eve3_7xx_pwrdm,
&emu_7xx_pwrdm,
&dsp2_7xx_pwrdm,
&dsp1_7xx_pwrdm,
&cam_7xx_pwrdm,
&eve4_7xx_pwrdm,
&eve2_7xx_pwrdm,
&eve1_7xx_pwrdm,
NULL
};
void __init dra7xx_powerdomains_init(void)
{
pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_dra7xx);
pwrdm_complete_init();
}
arch/arm/mach-omap2/prcm44xx.h
浏览文件 @ e3e1970f
......@@ -38,6 +38,11 @@
#define OMAP54XX_SCRM_PARTITION 4
#define OMAP54XX_PRCM_MPU_PARTITION 5
#define DRA7XX_PRM_PARTITION 1
#define DRA7XX_CM_CORE_AON_PARTITION 2
#define DRA7XX_CM_CORE_PARTITION 3
#define DRA7XX_MPU_PRCM_PARTITION 5
/*
* OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
* IDs, plus one
......
arch/arm/mach-omap2/prcm_mpu7xx.h 0 → 100644
浏览文件 @ e3e1970f
/*
* DRA7xx PRCM MPU instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
#include "prcm_mpu_44xx_54xx.h"
#define DRA7XX_PRCM_MPU_BASE 0x48243000
#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
/* MPU_PRCM instances */
#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
/* PRCM_MPU clockdomain register offsets (from instance start) */
#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
/* MPU_PRCM */
/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
#endif
arch/arm/mach-omap2/prm44xx.c
浏览文件 @ e3e1970f
......@@ -620,6 +620,15 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
return 0;
}
static int omap4_check_vcvp(void)
{
/* No VC/VP on dra7xx devices */
if (soc_is_dra7xx())
return 0;
return 1;
}
struct pwrdm_ops omap4_pwrdm_operations = {
.pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
......@@ -637,6 +646,7 @@ struct pwrdm_ops omap4_pwrdm_operations = {
.pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
.pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
.pwrdm_wait_transition = omap4_pwrdm_wait_transition,
.pwrdm_has_voltdm = omap4_check_vcvp,
};
/*
......@@ -650,7 +660,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
int __init omap44xx_prm_init(void)
{
if (!cpu_is_omap44xx() && !soc_is_omap54xx())
if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
return 0;
return prm_register(&omap44xx_prm_ll_data);
......
arch/arm/mach-omap2/prm7xx.h 0 → 100644
浏览文件 @ e3e1970f
此差异已折叠。
arch/arm/mach-omap2/prminst44xx.c
浏览文件 @ e3e1970f
此差异已折叠。
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