提交 e22e6d20 编写于 作者: A Alex Deucher 提交者: Dave Airlie

drm/radeon/kms: use correct BUS_CNTL reg on rs600

BUS_CNTL is at 0x30 on rs600, not 0x4c.
Signed-off-by: NAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>
上级 9a4a0b9c
...@@ -426,7 +426,7 @@ int rs600_gart_init(struct radeon_device *rdev) ...@@ -426,7 +426,7 @@ int rs600_gart_init(struct radeon_device *rdev)
return radeon_gart_table_vram_alloc(rdev); return radeon_gart_table_vram_alloc(rdev);
} }
int rs600_gart_enable(struct radeon_device *rdev) static int rs600_gart_enable(struct radeon_device *rdev)
{ {
u32 tmp; u32 tmp;
int r, i; int r, i;
...@@ -440,8 +440,8 @@ int rs600_gart_enable(struct radeon_device *rdev) ...@@ -440,8 +440,8 @@ int rs600_gart_enable(struct radeon_device *rdev)
return r; return r;
radeon_gart_restore(rdev); radeon_gart_restore(rdev);
/* Enable bus master */ /* Enable bus master */
tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
WREG32(R_00004C_BUS_CNTL, tmp); WREG32(RADEON_BUS_CNTL, tmp);
/* FIXME: setup default page */ /* FIXME: setup default page */
WREG32_MC(R_000100_MC_PT0_CNTL, WREG32_MC(R_000100_MC_PT0_CNTL,
(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
......
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