提交 e0d7ce78 编写于 作者: T Tony Cheng 提交者: Alex Deucher

drm/amd/display: enable clock gating and dchubp power gating

also refactor to clean reduce loc to achieve same logic
Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 f33ad37f
......@@ -145,7 +145,8 @@ struct dc_debug {
bool disable_stutter;
bool disable_dcc;
bool disable_dfs_bypass;
bool disable_power_gate;
bool disable_dpp_power_gate;
bool disable_hubp_power_gate;
bool disable_clock_gate;
bool disable_dmcu;
bool disable_color_module;
......
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