drm/amd/display: separate cm functions out from dcn10_dpp

Signed-off-by: NYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn10/Makefile

@@ -4,7 +4,7 @@
 DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
 		dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
 		dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o \
-		dcn10_dpp_dscl.o
+		dcn10_dpp_dscl.o dcn10_dpp_cm.o
 
 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

@@ -1387,6 +1387,40 @@ struct dcn10_dpp {
 	bool is_write_to_ram_a_safe;
 };
 
+void opp_program_regamma_lut(
+		struct transform *xfm_base,
+		const struct pwl_result_data *rgb,
+		uint32_t num);
+
+void oppn10_power_on_regamma_lut(
+	struct transform *xfm_base,
+	bool power_on);
+
+void opp_configure_regamma_lut(
+		struct transform *xfm_base,
+		bool is_ram_a);
+
+/*program re gamma RAM A*/
+void opp_program_regamma_luta_settings(
+		struct transform *xfm_base,
+		const struct pwl_params *params);
+
+/*program re gamma RAM B*/
+void opp_program_regamma_lutb_settings(
+		struct transform *xfm_base,
+		const struct pwl_params *params);
+void oppn10_set_output_csc_adjustment(
+		struct transform *xfm_base,
+		const struct out_csc_color_matrix *tbl_entry);
+
+void oppn10_set_output_csc_default(
+		struct transform *xfm_base,
+		const struct default_adjustment *default_adjust);
+
+void dcn_dpp_set_gamut_remap(
+	struct transform *xfm,
+	const struct xfm_grph_csc_adjustment *adjust);
+
 void dcn10_dpp_set_scaler_manual_scale(
 	struct transform *xfm_base,
 	const struct scaler_data *scl_data);