提交 d87d0c93 编写于 作者: R Ralf Baechle

[MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 61a33168
......@@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
" addu %1, %0, 1 \n"
" sc %1, %2 \n"
" beqz %1, 1b \n"
" sync \n"
__WEAK_LLSC_MB
: "=&r" (result), "=&r" (temp), "=m" (*pv)
: "m" (*pv)
: "memory");
......
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