提交 d863dc9e 编写于 作者: P Purna Chandra Mandal 提交者: Ralf Baechle

dt/bindings/clk: Add PIC32 clock binding documentation.

Document the devicetree bindings for the clock driver found on Microchip
PIC32 class devices.
Signed-off-by: NPurna Chandra Mandal <purna.mandal@microchip.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NMichael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Purna Chandra Mandal <purna.mandal@microchip.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13246/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 c9babb19
Microchip PIC32 Clock Controller Binding
----------------------------------------
Microchip clock controller is consists of few oscillators, PLL, multiplexer
and few divider modules.
This binding uses common clock bindings.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: shall be "microchip,pic32mzda-clk".
- reg: shall contain base address and length of clock registers.
- #clock-cells: shall be 1.
Optional properties:
- microchip,pic32mzda-sosc: shall be added only if platform has
secondary oscillator connected.
Example:
rootclk: clock-controller@1f801200 {
compatible = "microchip,pic32mzda-clk";
reg = <0x1f801200 0x200>;
#clock-cells = <1>;
/* optional */
microchip,pic32mzda-sosc;
};
The clock consumer shall specify the desired clock-output of the clock
controller (as defined in [2]) by specifying output-id in its "clock"
phandle cell.
[2] include/dt-bindings/clock/microchip,pic32-clock.h
For example for UART2:
uart2: serial@2 {
compatible = "microchip,pic32mzda-uart";
reg = <>;
interrupts = <>;
clocks = <&rootclk PB2CLK>;
};
/*
* Purna Chandra Mandal,<purna.mandal@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
/* clock output indices */
#define POSCCLK 0
#define FRCCLK 1
#define BFRCCLK 2
#define LPRCCLK 3
#define SOSCCLK 4
#define FRCDIVCLK 5
#define PLLCLK 6
#define SCLK 7
#define PB1CLK 8
#define PB2CLK 9
#define PB3CLK 10
#define PB4CLK 11
#define PB5CLK 12
#define PB6CLK 13
#define PB7CLK 14
#define REF1CLK 15
#define REF2CLK 16
#define REF3CLK 17
#define REF4CLK 18
#define REF5CLK 19
#define UPLLCLK 20
#define MAXCLKS 21
#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
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