arm: mvebu: add L2 cache support

Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-and-reviewed-by: NYehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: NLior Amsalem <alior@marvell.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

arch/arm/mach-mvebu/Kconfig

@@ -22,6 +22,7 @@ config MACH_ARMADA_370_XP
 	bool
 	select ARMADA_370_XP_TIMER
 	select HAVE_SMP
+	select CACHE_L2X0
 	select CPU_PJ4B
 
 config MACH_ARMADA_370

arch/arm/mach-mvebu/irq-armada-370-xp.c

@@ -25,6 +25,7 @@
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
 #include <asm/smp_plat.h>
+#include <asm/hardware/cache-l2x0.h>
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
@@ -210,4 +211,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
 void __init armada_370_xp_init_irq(void)
 {
 	of_irq_init(mpic_of_match);
+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
 }