clk: sunxi: add PLL5 and PLL6 support
This commit implements PLL5 and PLL6 support on the sunxi clock driver. These PLLs use a similar factor clock, but differ on their outputs. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Acked-by: NMike Turquette <mturquette@linaro.org>
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