提交 d2819f80 编写于 作者: A Arnd Bergmann

Merge branch 'spear/pinctrl' into spear/clock

Conflicts:
	arch/arm/mach-spear3xx/Makefile
	arch/arm/mach-spear3xx/clock.c
	arch/arm/mach-spear3xx/include/mach/generic.h
	arch/arm/mach-spear6xx/clock.c
	arch/arm/plat-spear/Makefile
	drivers/pinctrl/core.c

This resolves some annoying merge conflicts.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
......@@ -17,14 +17,14 @@ Introduction
SPEAr (Platform)
- SPEAr3XX (3XX SOC series, based on ARM9)
- SPEAr300 (SOC)
- SPEAr300_EVB (Evaluation Board)
- SPEAr300 Evaluation Board
- SPEAr310 (SOC)
- SPEAr310_EVB (Evaluation Board)
- SPEAr310 Evaluation Board
- SPEAr320 (SOC)
- SPEAr320_EVB (Evaluation Board)
- SPEAr320 Evaluation Board
- SPEAr6XX (6XX SOC series, based on ARM9)
- SPEAr600 (SOC)
- SPEAr600_EVB (Evaluation Board)
- SPEAr600 Evaluation Board
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
......@@ -51,10 +51,11 @@ Introduction
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
mach-spear* also contains board specific files for each machine type.
mach-spear* doesn't contains board specific files as they fully support
Flattened Device Tree.
Document Author
---------------
Viresh Kumar, (c) 2010 ST Microelectronics
Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
......@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
Required root node property:
compatible = "st,spear600";
Boards with the ST SPEAr300 SoC shall have the following properties:
Required root node property:
compatible = "st,spear300";
Boards with the ST SPEAr310 SoC shall have the following properties:
Required root node property:
compatible = "st,spear310";
Boards with the ST SPEAr320 SoC shall have the following properties:
Required root node property:
compatible = "st,spear320";
* Freescale IOMUX Controller (IOMUXC) for i.MX
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called ALT modes). Since different modules require
different PAD settings (like pull up, keeper, etc) the IOMUXC controls
also the PAD settings parameters.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Freescale IMX pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and config
of the pins in that group. The 'mux' selects the function mode(also named mux
mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, open drain, drive strength, etc.
Required properties for iomux controller:
- compatible: "fsl,<soc>-iomuxc"
Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
Required properties for pin configuration node:
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
pins and functions of each SoC.
Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.
SION(1 << 30): Software Input On Field.
Force the selected mux mode input path no matter of MUX_MODE functionality.
By default the input path is determined by functionality of the selected
mux mode (regular).
Other bits are used for PAD setting.
Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
of bits definitions.
NOTE:
Some requirements for using fsl,imx-pinctrl binding:
1. We have pin function node defined under iomux controller node to represent
what pinmux functions this SoC supports.
2. The pin configuration node intends to work on a specific function should
to be defined under that specific function node.
The function node's name should represent well about what function
this group of pins in this pin configuration node are working on.
3. The driver can use the function node's name and pin configuration node's
name describe the pin function and group hierarchy.
For example, Linux IMX pinctrl driver takes the function node's name
as the function name and pin configuration node's name as group name to
create the map table.
4. Each pin configuration node should have a phandle, devices can set pins
configurations by referring to the phandle of that pin configuration node.
Examples:
usdhc@0219c000 { /* uSDHC4 */
fsl,card-wired;
vmmc-supply = <&reg_3p3v>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
};
iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
/* shared pinctrl settings */
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
};
};
....
};
Refer to the IOMUXC controller chapter in imx6q datasheet,
0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
80Ohm driver strength and Fast Slew Rate.
User should refer to each SoC spec to set the correct value.
TODO: when dtc macro support is available, we can change above raw data
to dt macro which can get better readability in dts file.
NVIDIA Tegra20 pinmux controller
Required properties:
- compatible: "nvidia,tegra20-pinmux"
- reg: Should contain the register physical address and length for each of
the tri-state, mux, pull-up/down, and pad control register sets.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Tegra's pin configuration nodes act as a container for an abitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, tristate, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function or tristate parameter. For this
reason, even seemingly boolean values are actually tristates in this binding:
unspecified, off, or on. Unspecified is represented as an absent property,
and off/on are represented as integer values 0 and 1.
Required subnode-properties:
- nvidia,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- nvidia,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below. See the Tegra
TRM to determine which are valid for each pin or group.
- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
0: none, 1: down, 2: up.
- nvidia,tristate: Integer.
0: drive, 1: tristate.
- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
0: no, 1: yes.
- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
0: no, 1: yes.
- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
most power. Controls the drive power or current. See "Low Power Mode"
or "LPMD1" and "LPMD0" in the Tegra TRM.
- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
Tegra TRM.
- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
Tegra TRM.
- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
fastest. The range of valid values depends on the pingroup. See
"DRVDN_SLWR" in the Tegra TRM.
- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
fastest. The range of valid values depends on the pingroup. See
"DRVUP_SLWF" in the Tegra TRM.
Note that many of these properties are only valid for certain specific pins
or groups. See the Tegra TRM and various pinmux spreadsheets for complete
details regarding which groups support which functionality. The Linux pinctrl
driver may also be a useful reference, since it consolidates, disambiguates,
and corrects data from all those sources.
Valid values for pin and group names are:
mux groups:
These all support nvidia,function, nvidia,tristate, and many support
nvidia,pull.
ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
uca, ucb, uda.
tristate groups:
These only support nvidia,pull.
ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
ld19_18, ld21_20, ld23_22.
drive groups:
With some exceptions, these support nvidia,high-speed-mode,
nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
drive_uda.
Example:
pinctrl@70000000 {
compatible = "nvidia,tegra20-pinmux";
reg = < 0x70000014 0x10 /* Tri-state registers */
0x70000080 0x20 /* Mux registers */
0x700000a0 0x14 /* Pull-up/down registers */
0x70000868 0xa8 >; /* Pad control registers */
};
Example board file extract:
pinctrl@70000000 {
sdio4_default: sdio4_default {
atb {
nvidia,pins = "atb", "gma", "gme";
nvidia,function = "sdio4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
};
};
sdhci@c8000600 {
pinctrl-names = "default";
pinctrl-0 = <&sdio4_default>;
};
NVIDIA Tegra30 pinmux controller
The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
that binding as a baseline, and only documents the differences between the
two bindings.
Required properties:
- compatible: "nvidia,tegra30-pinmux"
- reg: Should contain the register physical address and length for each of
the pad control and mux registers.
Tegra30 adds the following optional properties for pin configuration subnodes:
- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
- nvidia,lock: Integer. Lock the pin configuration against further changes
until reset. 0: no, 1: yes.
- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
As with Tegra20, see the Tegra TRM for complete details regarding which groups
support which functionality.
Valid values for pin and group names are:
per-pin mux groups:
These all support nvidia,function, nvidia,tristate, nvidia,pull,
nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
nvidia,io-reset.
clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
pwr_int_n.
drive groups:
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
uart3, uda, vi1.
Example:
pinctrl@70000000 {
compatible = "nvidia,tegra30-pinmux";
reg = < 0x70000868 0xd0 /* Pad control registers */
0x70003000 0x3e0 >; /* Mux registers */
};
Example board file extract:
pinctrl@70000000 {
sdmmc4_default: pinmux {
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
};
};
sdhci@78000400 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc4_default>;
};
== Introduction ==
Hardware modules that control pin multiplexing or configuration parameters
such as pull-up/down, tri-state, drive-strength etc are designated as pin
controllers. Each pin controller must be represented as a node in device tree,
just like any other hardware module.
Hardware modules whose signals are affected by pin configuration are
designated client devices. Again, each client device must be represented as a
node in device tree, just like any other hardware module.
For a client device to operate correctly, certain pin controllers must
set up certain specific pin configurations. Some client devices need a
single static pin configuration, e.g. set up during initialization. Others
need to reconfigure pins at run-time, for example to tri-state pins when the
device is inactive. Hence, each client device can define a set of named
states. The number and names of those states is defined by the client device's
own binding.
The common pinctrl bindings defined in this file provide an infrastructure
for client device device tree nodes to map those state names to the pin
configuration used by those states.
Note that pin controllers themselves may also be client devices of themselves.
For example, a pin controller may set up its own "active" state when the
driver loads. This would allow representing a board's static pin configuration
in a single place, rather than splitting it across multiple client device
nodes. The decision to do this or not somewhat rests with the author of
individual board device tree files, and any requirements imposed by the
bindings for the individual client devices in use by that board, i.e. whether
they require certain specific named states for dynamic pin configuration.
== Pinctrl client devices ==
For each client device individually, every pin state is assigned an integer
ID. These numbers start at 0, and are contiguous. For each state ID, a unique
property exists to define the pin configuration. Each state may also be
assigned a name. When names are used, another property exists to map from
those names to the integer IDs.
Each client device's own binding determines the set of states the must be
defined in its device tree node, and whether to define the set of state
IDs that must be provided, or whether to define the set of state names that
must be provided.
Required properties:
pinctrl-0: List of phandles, each pointing at a pin configuration
node. These referenced pin configuration nodes must be child
nodes of the pin controller that they configure. Multiple
entries may exist in this list so that multiple pin
controllers may be configured, or so that a state may be built
from multiple nodes for a single pin controller, each
contributing part of the overall configuration. See the next
section of this document for details of the format of these
pin configuration nodes.
In some cases, it may be useful to define a state, but for it
to be empty. This may be required when a common IP block is
used in an SoC either without a pin controller, or where the
pin controller does not affect the HW module in question. If
the binding for that IP block requires certain pin states to
exist, they must still be defined, but may be left empty.
Optional properties:
pinctrl-1: List of phandles, each pointing at a pin configuration
node within a pin controller.
...
pinctrl-n: List of phandles, each pointing at a pin configuration
node within a pin controller.
pinctrl-names: The list of names to assign states. List entry 0 defines the
name for integer state ID 0, list entry 1 for state ID 1, and
so on.
For example:
/* For a client device requiring named states */
device {
pinctrl-names = "active", "idle";
pinctrl-0 = <&state_0_node_a>;
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
};
/* For the same device if using state IDs */
device {
pinctrl-0 = <&state_0_node_a>;
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
};
/*
* For an IP block whose binding supports pin configuration,
* but in use on an SoC that doesn't have any pin control hardware
*/
device {
pinctrl-names = "active", "idle";
pinctrl-0 = <>;
pinctrl-1 = <>;
};
== Pin controller devices ==
Pin controller devices should contain the pin configuration nodes that client
devices reference.
For example:
pincontroller {
... /* Standard DT properties for the device itself elided */
state_0_node_a {
...
};
state_1_node_a {
...
};
state_1_node_b {
...
};
}
The contents of each of those pin configuration child nodes is defined
entirely by the binding for the individual pin controller device. There
exists no common standard for this content.
The pin configuration nodes need not be direct children of the pin controller
device; they may be grandchildren, for example. Whether this is legal, and
whether there is any interaction between the child and intermediate parent
nodes, is again defined entirely by the binding for the individual pin
controller device.
ST Microelectronics, SPEAr pinmux controller
Required properties:
- compatible : "st,spear300-pinmux"
: "st,spear310-pinmux"
: "st,spear320-pinmux"
- reg : Address range of the pinctrl registers
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
- Its values for SPEAr300:
- NAND_MODE : <0>
- NOR_MODE : <1>
- PHOTO_FRAME_MODE : <2>
- LEND_IP_PHONE_MODE : <3>
- HEND_IP_PHONE_MODE : <4>
- LEND_WIFI_PHONE_MODE : <5>
- HEND_WIFI_PHONE_MODE : <6>
- ATA_PABX_WI2S_MODE : <7>
- ATA_PABX_I2S_MODE : <8>
- CAML_LCDW_MODE : <9>
- CAMU_LCD_MODE : <10>
- CAMU_WLCD_MODE : <11>
- CAML_LCD_MODE : <12>
- Its values for SPEAr320:
- AUTO_NET_SMII_MODE : <0>
- AUTO_NET_MII_MODE : <1>
- AUTO_EXP_MODE : <2>
- SMALL_PRINTERS_MODE : <3>
- EXTENDED_MODE : <4>
Please refer to pinctrl-bindings.txt in this directory for details of the common
pinctrl bindings used by client devices.
SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
of these subnodes represents muxing for a pin, a group, or a list of pins or
groups.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Required subnode-properties:
- st,pins : An array of strings. Each string contains the name of a pin or
group.
- st,function: A string containing the name of the function to mux to the pin or
group. See the SPEAr's TRM to determine which are valid for each pin or group.
Valid values for group and function names can be found from looking at the
group and function arrays in driver files:
drivers/pinctrl/spear/pinctrl-spear3*0.c
Valid values for group names are:
For All SPEAr3xx machines:
"firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
"gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
"gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
"timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
For SPEAr300 machines:
"fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
"clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
"dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
"gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
For SPEAr310 machines:
"emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
"uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
For SPEAr320 machines:
"clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
"sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
"uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
"uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
"uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
"uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
"uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
"uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
"uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
"uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
"can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
"pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
"pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
"pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
"pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
"pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
"pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
"ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
"ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
"ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
Valid values for function names are:
For All SPEAr3xx machines:
"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
"uart0", "timer_0_1", "timer_2_3"
For SPEAr300 machines:
"fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
For SPEAr310 machines:
"emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
"rs485_1", "tdm"
For SPEAr320 machines:
"clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
"mii0_1", "i2c1", "i2c2"
NVIDIA Tegra 2 pinmux controller
Required properties:
- compatible : "nvidia,tegra20-pinmux"
......@@ -280,3 +280,7 @@ REGULATOR
CLOCK
devm_clk_get()
devm_clk_put()
PINCTRL
devm_pinctrl_get()
devm_pinctrl_put()
......@@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
};
static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
static int foo_get_groups_count(struct pinctrl_dev *pctldev)
{
if (selector >= ARRAY_SIZE(foo_groups))
return -EINVAL;
return 0;
return ARRAY_SIZE(foo_groups);
}
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
......@@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
}
static struct pinctrl_ops foo_pctrl_ops = {
.list_groups = foo_list_groups,
.get_groups_count = foo_get_groups_count,
.get_group_name = foo_get_group_name,
.get_group_pins = foo_get_group_pins,
};
......@@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
.pctlops = &foo_pctrl_ops,
};
The pin control subsystem will call the .list_groups() function repeatedly
beginning on 0 until it returns non-zero to determine legal selectors, then
it will call the other functions to retrieve the name and pins of the group.
Maintaining the data structure of the groups is up to the driver, this is
just a simple example - in practice you may need more entries in your group
structure, for example specific register ranges associated with each group
and so on.
The pin control subsystem will call the .get_groups_count() function to
determine total number of legal selectors, then it will call the other functions
to retrieve the name and pins of the group. Maintaining the data structure of
the groups is up to the driver, this is just a simple example - in practice you
may need more entries in your group structure, for example specific register
ranges associated with each group and so on.
Pin configuration
......@@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
};
static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
static int foo_get_groups_count(struct pinctrl_dev *pctldev)
{
if (selector >= ARRAY_SIZE(foo_groups))
return -EINVAL;
return 0;
return ARRAY_SIZE(foo_groups);
}
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
......@@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
}
static struct pinctrl_ops foo_pctrl_ops = {
.list_groups = foo_list_groups,
.get_groups_count = foo_get_groups_count,
.get_group_name = foo_get_group_name,
.get_group_pins = foo_get_group_pins,
};
......@@ -640,7 +635,7 @@ struct foo_pmx_func {
const unsigned num_groups;
};
static const char * const spi0_groups[] = { "spi0_1_grp" };
static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
static const char * const i2c0_groups[] = { "i2c0_grp" };
static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
"mmc0_3_grp" };
......@@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
},
};
int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
int foo_get_functions_count(struct pinctrl_dev *pctldev)
{
if (selector >= ARRAY_SIZE(foo_functions))
return -EINVAL;
return 0;
return ARRAY_SIZE(foo_functions);
}
const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
......@@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
}
struct pinmux_ops foo_pmxops = {
.list_functions = foo_list_funcs,
.get_functions_count = foo_get_functions_count,
.get_function_name = foo_get_fname,
.get_function_groups = foo_get_groups,
.enable = foo_enable,
......@@ -786,7 +779,7 @@ and spi on the second function mapping:
#include <linux/pinctrl/machine.h>
static const struct pinctrl_map __initdata mapping[] = {
static const struct pinctrl_map mapping[] __initconst = {
{
.dev_name = "foo-spi.0",
.name = PINCTRL_STATE_DEFAULT,
......@@ -952,13 +945,13 @@ case), we define a mapping like this:
The result of grabbing this mapping from the device with something like
this (see next paragraph):
p = pinctrl_get(dev);
p = devm_pinctrl_get(dev);
s = pinctrl_lookup_state(p, "8bit");
ret = pinctrl_select_state(p, s);
or more simply:
p = pinctrl_get_select(dev, "8bit");
p = devm_pinctrl_get_select(dev, "8bit");
Will be that you activate all the three bottom records in the mapping at
once. Since they share the same name, pin controller device, function and
......@@ -992,7 +985,7 @@ foo_probe()
/* Allocate a state holder named "foo" etc */
struct foo_state *foo = ...;
foo->p = pinctrl_get(&device);
foo->p = devm_pinctrl_get(&device);
if (IS_ERR(foo->p)) {
/* FIXME: clean up "foo" here */
return PTR_ERR(foo->p);
......@@ -1000,24 +993,17 @@ foo_probe()
foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
if (IS_ERR(foo->s)) {
pinctrl_put(foo->p);
/* FIXME: clean up "foo" here */
return PTR_ERR(s);
}
ret = pinctrl_select_state(foo->s);
if (ret < 0) {
pinctrl_put(foo->p);
/* FIXME: clean up "foo" here */
return ret;
}
}
foo_remove()
{
pinctrl_put(state->p);
}
This get/lookup/select/put sequence can just as well be handled by bus drivers
if you don't want each and every driver to handle it and you know the
arrangement on your bus.
......@@ -1029,6 +1015,11 @@ The semantics of the pinctrl APIs are:
kernel memory to hold the pinmux state. All mapping table parsing or similar
slow operations take place within this API.
- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
to be called automatically on the retrieved pointer when the associated
device is removed. It is recommended to use this function over plain
pinctrl_get().
- pinctrl_lookup_state() is called in process context to obtain a handle to a
specific state for a the client device. This operation may be slow too.
......@@ -1041,14 +1032,30 @@ The semantics of the pinctrl APIs are:
- pinctrl_put() frees all information associated with a pinctrl handle.
- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
explicitly destroy a pinctrl object returned by devm_pinctrl_get().
However, use of this function will be rare, due to the automatic cleanup
that will occur even without calling it.
pinctrl_get() must be paired with a plain pinctrl_put().
pinctrl_get() may not be paired with devm_pinctrl_put().
devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
devm_pinctrl_get() may not be paired with plain pinctrl_put().
Usually the pin control core handled the get/put pair and call out to the
device drivers bookkeeping operations, like checking available functions and
the associated pins, whereas the enable/disable pass on to the pin controller
driver which takes care of activating and/or deactivating the mux setting by
quickly poking some registers.
The pins are allocated for your device when you issue the pinctrl_get() call,
after this you should be able to see this in the debugfs listing of all pins.
The pins are allocated for your device when you issue the devm_pinctrl_get()
call, after this you should be able to see this in the debugfs listing of all
pins.
NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
requested pinctrl handles, for example if the pinctrl driver has not yet
registered. Thus make sure that the error path in your driver gracefully
cleans up and is ready to retry the probing later in the startup process.
System pin control hogging
......@@ -1094,13 +1101,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
#include <linux/pinctrl/consumer.h>
foo_switch()
{
struct pinctrl *p;
struct pinctrl_state *s1, *s2;
struct pinctrl *p;
struct pinctrl_state *s1, *s2;
foo_probe()
{
/* Setup */
p = pinctrl_get(&device);
p = devm_pinctrl_get(&device);
if (IS_ERR(p))
...
......@@ -1111,7 +1118,10 @@ foo_switch()
s2 = pinctrl_lookup_state(foo->p, "pos-B");
if (IS_ERR(s2))
...
}
foo_switch()
{
/* Enable on position A */
ret = pinctrl_select_state(s1);
if (ret < 0)
......@@ -1125,8 +1135,6 @@ foo_switch()
...
...
pinctrl_put(p);
}
The above has to be done from process context.
......@@ -5244,6 +5244,14 @@ M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
F: drivers/pinctrl/
PIN CONTROLLER - ST SPEAR
M: Viresh Kumar <viresh.kumar@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: driver/pinctrl/spear/
PKTCDVD DRIVER
M: Peter Osterlund <petero2@telia.com>
S: Maintained
......@@ -6338,21 +6346,6 @@ W: http://www.st.com/spear
S: Maintained
F: drivers/clk/spear/
SPEAR PAD MULTIPLEXING SUPPORT
M: Viresh Kumar <viresh.kumar@st.com>
L: spear-devel@list.st.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.st.com/spear
S: Maintained
F: arch/arm/plat-spear/include/plat/padmux.h
F: arch/arm/plat-spear/padmux.c
F: arch/arm/mach-spear*/spear*xx.c
F: arch/arm/mach-spear*/include/mach/generic.h
F: arch/arm/mach-spear3xx/spear3*0.c
F: arch/arm/mach-spear3xx/spear3*0_evb.c
F: arch/arm/mach-spear6xx/spear600.c
F: arch/arm/mach-spear6xx/spear600_evb.c
SPI SUBSYSTEM
M: Grant Likely <grant.likely@secretlab.ca>
L: spi-devel-general@lists.sourceforge.net
......
/*
* DTS file for SPEAr300 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear300.dtsi"
/ {
model = "ST SPEAr300 Evaluation Board";
compatible = "st,spear300-evb", "st,spear300";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@99000000 {
st,pinmux-mode = <2>;
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
ssp0 {
st,pins = "ssp0_grp";
st,function = "ssp0";
};
mii0 {
st,pins = "mii0_grp";
st,function = "mii0";
};
uart0 {
st,pins = "uart0_grp";
st,function = "uart0";
};
clcd {
st,pins = "clcd_pfmode_grp";
st,function = "clcd";
};
sdhci {
st,pins = "sdhci_4bit_grp";
st,function = "sdhci";
};
gpio1 {
st,pins = "gpio1_4_to_7_grp",
"gpio1_0_to_3_grp";
st,function = "gpio1";
};
};
};
clcd@60000000 {
status = "okay";
};
dma@fc400000 {
status = "okay";
};
fsmc: flash@94000000 {
status = "okay";
};
gmac: eth@e0800000 {
status = "okay";
};
sdhci@70000000 {
int-gpio = <&gpio1 0 0>;
power-gpio = <&gpio1 2 1>;
status = "okay";
};
smi: flash@fc000000 {
status = "okay";
};
spi0: spi@d0100000 {
status = "okay";
};
ehci@e1800000 {
status = "okay";
};
ohci@e1900000 {
status = "okay";
};
ohci@e2100000 {
status = "okay";
};
apb {
gpio0: gpio@fc980000 {
status = "okay";
};
gpio1: gpio@a9000000 {
status = "okay";
};
i2c0: i2c@d0180000 {
status = "okay";
};
kbd@a0000000 {
linux,keymap = < 0x00010000
0x00020100
0x00030200
0x00040300
0x00050400
0x00060500
0x00070600
0x00080700
0x00090800
0x000a0001
0x000c0101
0x000d0201
0x000e0301
0x000f0401
0x00100501
0x00110601
0x00120701
0x00130801
0x00140002
0x00150102
0x00160202
0x00170302
0x00180402
0x00190502
0x001a0602
0x001b0702
0x001c0802
0x001d0003
0x001e0103
0x001f0203
0x00200303
0x00210403
0x00220503
0x00230603
0x00240703
0x00250803
0x00260004
0x00270104
0x00280204
0x00290304
0x002a0404
0x002b0504
0x002c0604
0x002d0704
0x002e0804
0x002f0005
0x00300105
0x00310205
0x00320305
0x00330405
0x00340505
0x00350605
0x00360705
0x00370805
0x00380006
0x00390106
0x003a0206
0x003b0306
0x003c0406
0x003d0506
0x003e0606
0x003f0706
0x00400806
0x00410007
0x00420107
0x00430207
0x00440307
0x00450407
0x00460507
0x00470607
0x00480707
0x00490807
0x004a0008
0x004b0108
0x004c0208
0x004d0308
0x004e0408
0x004f0508
0x00500608
0x00510708
0x00520808 >;
autorepeat;
st,mode = <0>;
status = "okay";
};
rtc@fc900000 {
status = "okay";
};
serial@d0000000 {
status = "okay";
};
wdt@fc880000 {
status = "okay";
};
};
};
};
/*
* DTS file for SPEAr300 SoC
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear3xx.dtsi"
/ {
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x60000000 0x60000000 0x50000000
0xd0000000 0xd0000000 0x30000000>;
pinmux@99000000 {
compatible = "st,spear300-pinmux";
reg = <0x99000000 0x1000>;
};
clcd@60000000 {
compatible = "arm,clcd-pl110", "arm,primecell";
reg = <0x60000000 0x1000>;
interrupts = <30>;
status = "disabled";
};
fsmc: flash@94000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x94000000 0x1000 /* FSMC Register */
0x80000000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
status = "disabled";
};
sdhci@70000000 {
compatible = "st,sdhci-spear";
reg = <0x70000000 0x100>;
interrupts = <1>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xa0000000 0xa0000000 0x10000000
0xd0000000 0xd0000000 0x30000000>;
gpio1: gpio@a9000000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xa9000000 0x1000>;
status = "disabled";
};
kbd@a0000000 {
compatible = "st,spear300-kbd";
reg = <0xa0000000 0x1000>;
status = "disabled";
};
};
};
};
/*
* DTS file for SPEAr310 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear310.dtsi"
/ {
model = "ST SPEAr310 Evaluation Board";
compatible = "st,spear310-evb", "st,spear310";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@b4000000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
gpio0 {
st,pins = "gpio0_pin0_grp",
"gpio0_pin1_grp",
"gpio0_pin2_grp",
"gpio0_pin3_grp",
"gpio0_pin4_grp",
"gpio0_pin5_grp";
st,function = "gpio0";
};
i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
mii0 {
st,pins = "mii0_grp";
st,function = "mii0";
};
ssp0 {
st,pins = "ssp0_grp";
st,function = "ssp0";
};
uart0 {
st,pins = "uart0_grp";
st,function = "uart0";
};
emi {
st,pins = "emi_cs_0_to_5_grp";
st,function = "emi";
};
fsmc {
st,pins = "fsmc_grp";
st,function = "fsmc";
};
uart1 {
st,pins = "uart1_grp";
st,function = "uart1";
};
uart2 {
st,pins = "uart2_grp";
st,function = "uart2";
};
uart3 {
st,pins = "uart3_grp";
st,function = "uart3";
};
uart4 {
st,pins = "uart4_grp";
st,function = "uart4";
};
uart5 {
st,pins = "uart5_grp";
st,function = "uart5";
};
};
};
dma@fc400000 {
status = "okay";
};
fsmc: flash@44000000 {
status = "okay";
};
gmac: eth@e0800000 {
status = "okay";
};
smi: flash@fc000000 {
status = "okay";
clock-rate=<50000000>;
flash@f8000000 {
label = "m25p64";
reg = <0xf8000000 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
st,smi-fast-mode;
};
};
spi0: spi@d0100000 {
status = "okay";
};
ehci@e1800000 {
status = "okay";
};
ohci@e1900000 {
status = "okay";
};
ohci@e2100000 {
status = "okay";
};
apb {
gpio0: gpio@fc980000 {
status = "okay";
};
i2c0: i2c@d0180000 {
status = "okay";
};
rtc@fc900000 {
status = "okay";
};
serial@d0000000 {
status = "okay";
};
serial@b2000000 {
status = "okay";
};
serial@b2080000 {
status = "okay";
};
serial@b2100000 {
status = "okay";
};
serial@b2180000 {
status = "okay";
};
serial@b2200000 {
status = "okay";
};
wdt@fc880000 {
status = "okay";
};
};
};
};
/*
* DTS file for SPEAr310 SoC
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear3xx.dtsi"
/ {
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x40000000 0x40000000 0x10000000
0xb0000000 0xb0000000 0x10000000
0xd0000000 0xd0000000 0x30000000>;
pinmux@b4000000 {
compatible = "st,spear310-pinmux";
reg = <0xb4000000 0x1000>;
};
fsmc: flash@44000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x44000000 0x1000 /* FSMC Register */
0x40000000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
st,ale-off = <0x10000>;
st,cle-off = <0x20000>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xb0000000 0xb0000000 0x10000000
0xd0000000 0xd0000000 0x30000000>;
serial@b2000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2000000 0x1000>;
status = "disabled";
};
serial@b2080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2080000 0x1000>;
status = "disabled";
};
serial@b2100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2100000 0x1000>;
status = "disabled";
};
serial@b2180000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2180000 0x1000>;
status = "disabled";
};
serial@b2200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2200000 0x1000>;
status = "disabled";
};
};
};
};
/*
* DTS file for SPEAr320 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear320.dtsi"
/ {
model = "ST SPEAr300 Evaluation Board";
compatible = "st,spear300-evb", "st,spear300";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
pinmux@b3000000 {
st,pinmux-mode = <3>;
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
mii0 {
st,pins = "mii0_grp";
st,function = "mii0";
};
ssp0 {
st,pins = "ssp0_grp";
st,function = "ssp0";
};
uart0 {
st,pins = "uart0_grp";
st,function = "uart0";
};
sdhci {
st,pins = "sdhci_cd_51_grp";
st,function = "sdhci";
};
i2s {
st,pins = "i2s_grp";
st,function = "i2s";
};
uart1 {
st,pins = "uart1_grp";
st,function = "uart1";
};
uart2 {
st,pins = "uart2_grp";
st,function = "uart2";
};
can0 {
st,pins = "can0_grp";
st,function = "can0";
};
can1 {
st,pins = "can1_grp";
st,function = "can1";
};
mii2 {
st,pins = "mii2_grp";
st,function = "mii2";
};
pwm0_1 {
st,pins = "pwm0_1_pin_14_15_grp";
st,function = "pwm0_1";
};
pwm2 {
st,pins = "pwm2_pin_13_grp";
st,function = "pwm2";
};
};
};
clcd@90000000 {
status = "okay";
};
dma@fc400000 {
status = "okay";
};
fsmc: flash@4c000000 {
status = "okay";
};
gmac: eth@e0800000 {
status = "okay";
};
sdhci@70000000 {
power-gpio = <&gpio0 2 1>;
power_always_enb;
status = "okay";
};
smi: flash@fc000000 {
status = "okay";
};
spi0: spi@d0100000 {
status = "okay";
};
spi1: spi@a5000000 {
status = "okay";
};
spi2: spi@a6000000 {
status = "okay";
};
ehci@e1800000 {
status = "okay";
};
ohci@e1900000 {
status = "okay";
};
ohci@e2100000 {
status = "okay";
};
apb {
gpio0: gpio@fc980000 {
status = "okay";
};
i2c0: i2c@d0180000 {
status = "okay";
};
i2c1: i2c@a7000000 {
status = "okay";
};
rtc@fc900000 {
status = "okay";
};
serial@d0000000 {
status = "okay";
};
serial@a3000000 {
status = "okay";
};
serial@a4000000 {
status = "okay";
};
wdt@fc880000 {
status = "okay";
};
};
};
};
/*
* DTS file for SPEAr320 SoC
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear3xx.dtsi"
/ {
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x40000000 0x40000000 0x80000000
0xd0000000 0xd0000000 0x30000000>;
pinmux@b3000000 {
compatible = "st,spear320-pinmux";
reg = <0xb3000000 0x1000>;
};
clcd@90000000 {
compatible = "arm,clcd-pl110", "arm,primecell";
reg = <0x90000000 0x1000>;
interrupts = <33>;
status = "disabled";
};
fsmc: flash@4c000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x4c000000 0x1000 /* FSMC Register */
0x50000000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
status = "disabled";
};
sdhci@70000000 {
compatible = "st,sdhci-spear";
reg = <0x70000000 0x100>;
interrupts = <29>;
status = "disabled";
};
spi1: spi@a5000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa5000000 0x1000>;
status = "disabled";
};
spi2: spi@a6000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa6000000 0x1000>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xa0000000 0xa0000000 0x10000000
0xd0000000 0xd0000000 0x30000000>;
i2c1: i2c@a7000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xa7000000 0x1000>;
status = "disabled";
};
serial@a3000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xa3000000 0x1000>;
status = "disabled";
};
serial@a4000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xa4000000 0x1000>;
status = "disabled";
};
};
};
};
/*
* DTS file for all SPEAr3xx SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&vic>;
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xd0000000 0xd0000000 0x30000000>;
vic: interrupt-controller@f1100000 {
compatible = "arm,pl190-vic";
interrupt-controller;
reg = <0xf1100000 0x1000>;
#interrupt-cells = <1>;
};
dma@fc400000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0xfc400000 0x1000>;
interrupt-parent = <&vic>;
interrupts = <8>;
status = "disabled";
};
gmac: eth@e0800000 {
compatible = "st,spear600-gmac";
reg = <0xe0800000 0x8000>;
interrupts = <23 22>;
interrupt-names = "macirq", "eth_wake_irq";
status = "disabled";
};
smi: flash@fc000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xfc000000 0x1000>;
interrupts = <9>;
status = "disabled";
};
spi0: spi@d0100000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xd0100000 0x1000>;
interrupts = <20>;
status = "disabled";
};
ehci@e1800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe1800000 0x1000>;
interrupts = <26>;
status = "disabled";
};
ohci@e1900000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe1900000 0x1000>;
interrupts = <25>;
status = "disabled";
};
ohci@e2100000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe2100000 0x1000>;
interrupts = <27>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xd0000000 0xd0000000 0x30000000>;
gpio0: gpio@fc980000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xfc980000 0x1000>;
interrupts = <11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
i2c0: i2c@d0180000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xd0180000 0x1000>;
interrupts = <21>;
status = "disabled";
};
rtc@fc900000 {
compatible = "st,spear-rtc";
reg = <0xfc900000 0x1000>;
interrupts = <10>;
status = "disabled";
};
serial@d0000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xd0000000 0x1000>;
interrupts = <19>;
status = "disabled";
};
wdt@fc880000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0xfc880000 0x1000>;
interrupts = <12>;
status = "disabled";
};
};
};
};
......@@ -24,6 +24,10 @@
};
ahb {
dma@fc400000 {
status = "okay";
};
gmac: ethernet@e0800000 {
phy-mode = "gmii";
status = "okay";
......
......@@ -45,6 +45,14 @@
#interrupt-cells = <1>;
};
dma@fc400000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0xfc400000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <10>;
status = "disabled";
};
gmac: ethernet@e0800000 {
compatible = "st,spear600-gmac";
reg = <0xe0800000 0x8000>;
......
......@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_PLAT_SPEAR=y
CONFIG_BOARD_SPEAR300_EVB=y
CONFIG_BOARD_SPEAR310_EVB=y
CONFIG_BOARD_SPEAR320_EVB=y
CONFIG_MACH_SPEAR300=y
CONFIG_MACH_SPEAR310=y
CONFIG_MACH_SPEAR320=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_STMMAC_ETH=y
# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_SPEAR=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=8192
CONFIG_I2C=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SPEAR=y
CONFIG_RTC_CLASS=y
CONFIG_DMADEVICES=y
CONFIG_AMBA_PL08X=y
CONFIG_DMATEST=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
......@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
......@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
# CONFIG_CRC32 is not set
......@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_PLAT_SPEAR=y
CONFIG_ARCH_SPEAR6XX=y
CONFIG_BOARD_SPEAR600_EVB=y
CONFIG_BOARD_SPEAR600_DT=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_STMMAC_ETH=y
# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=8192
CONFIG_I2C=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PL061=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_ARM_SP805_WATCHDOG=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_RTC_CLASS=y
CONFIG_DMADEVICES=y
CONFIG_AMBA_PL08X=y
CONFIG_DMATEST=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_SECURITY=y
......@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_TMPFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=m
......@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
# CONFIG_CRC32 is not set
......@@ -5,39 +5,22 @@
if ARCH_SPEAR3XX
menu "SPEAr3xx Implementations"
config BOARD_SPEAR300_EVB
bool "SPEAr300 Evaluation Board"
select MACH_SPEAR300
help
Supports ST SPEAr300 Evaluation Board
config BOARD_SPEAR310_EVB
bool "SPEAr310 Evaluation Board"
select MACH_SPEAR310
help
Supports ST SPEAr310 Evaluation Board
config BOARD_SPEAR320_EVB
bool "SPEAr320 Evaluation Board"
select MACH_SPEAR320
help
Supports ST SPEAr320 Evaluation Board
endmenu
config MACH_SPEAR300
bool "SPEAr300"
bool "SPEAr300 Machine support with Device Tree"
select PINCTRL_SPEAR300
help
Supports ST SPEAr300 Machine
Supports ST SPEAr300 machine configured via the device-tree
config MACH_SPEAR310
bool "SPEAr310"
bool "SPEAr310 Machine support with Device Tree"
select PINCTRL_SPEAR310
help
Supports ST SPEAr310 Machine
Supports ST SPEAr310 machine configured via the device-tree
config MACH_SPEAR320
bool "SPEAr320"
bool "SPEAr320 Machine support with Device Tree"
select PINCTRL_SPEAR320
help
Supports ST SPEAr320 Machine
Supports ST SPEAr320 machine configured via the device-tree
endmenu
endif #ARCH_SPEAR3XX
......@@ -3,24 +3,13 @@
#
# common files
obj-y += spear3xx.o
obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
# spear300 specific files
obj-$(CONFIG_MACH_SPEAR300) += spear300.o
# spear300 boards files
obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
# spear310 specific files
obj-$(CONFIG_MACH_SPEAR310) += spear310.o
# spear310 boards files
obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
# spear320 specific files
obj-$(CONFIG_MACH_SPEAR320) += spear320.o
# spear320 boards files
obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb
dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb
dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb
......@@ -14,12 +14,12 @@
#ifndef __MACH_GENERIC_H
#define __MACH_GENERIC_H
#include <linux/amba/pl08x.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <plat/padmux.h>
/* spear3xx declarations */
/*
......@@ -31,171 +31,16 @@
#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
/* Add spear3xx family device structure declarations here */
extern struct amba_device spear3xx_gpio_device;
extern struct amba_device spear3xx_uart_device;
extern struct sys_timer spear3xx_timer;
extern struct pl022_ssp_controller pl022_plat_data;
extern struct pl08x_platform_data pl080_plat_data;
/* Add spear3xx family function declarations here */
void __init spear_setup_timer(void);
void __init spear3xx_clk_init(void);
void __init spear3xx_map_io(void);
void __init spear3xx_init_irq(void);
void __init spear3xx_init(void);
void __init spear3xx_dt_init_irq(void);
void spear_restart(char, const char *);
/* pad mux declarations */
#define PMX_FIRDA_MASK (1 << 14)
#define PMX_I2C_MASK (1 << 13)
#define PMX_SSP_CS_MASK (1 << 12)
#define PMX_SSP_MASK (1 << 11)
#define PMX_MII_MASK (1 << 10)
#define PMX_GPIO_PIN0_MASK (1 << 9)
#define PMX_GPIO_PIN1_MASK (1 << 8)
#define PMX_GPIO_PIN2_MASK (1 << 7)
#define PMX_GPIO_PIN3_MASK (1 << 6)
#define PMX_GPIO_PIN4_MASK (1 << 5)
#define PMX_GPIO_PIN5_MASK (1 << 4)
#define PMX_UART0_MODEM_MASK (1 << 3)
#define PMX_UART0_MASK (1 << 2)
#define PMX_TIMER_3_4_MASK (1 << 1)
#define PMX_TIMER_1_2_MASK (1 << 0)
/* pad mux devices */
extern struct pmx_dev spear3xx_pmx_firda;
extern struct pmx_dev spear3xx_pmx_i2c;
extern struct pmx_dev spear3xx_pmx_ssp_cs;
extern struct pmx_dev spear3xx_pmx_ssp;
extern struct pmx_dev spear3xx_pmx_mii;
extern struct pmx_dev spear3xx_pmx_gpio_pin0;
extern struct pmx_dev spear3xx_pmx_gpio_pin1;
extern struct pmx_dev spear3xx_pmx_gpio_pin2;
extern struct pmx_dev spear3xx_pmx_gpio_pin3;
extern struct pmx_dev spear3xx_pmx_gpio_pin4;
extern struct pmx_dev spear3xx_pmx_gpio_pin5;
extern struct pmx_dev spear3xx_pmx_uart0_modem;
extern struct pmx_dev spear3xx_pmx_uart0;
extern struct pmx_dev spear3xx_pmx_timer_3_4;
extern struct pmx_dev spear3xx_pmx_timer_1_2;
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
/* padmux plgpio devices */
extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
extern struct pmx_dev spear3xx_pmx_plgpio_28;
extern struct pmx_dev spear3xx_pmx_plgpio_29;
extern struct pmx_dev spear3xx_pmx_plgpio_30;
extern struct pmx_dev spear3xx_pmx_plgpio_31;
extern struct pmx_dev spear3xx_pmx_plgpio_32;
extern struct pmx_dev spear3xx_pmx_plgpio_33;
extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
#endif
/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
/* Add spear300 machine device structure declarations here */
extern struct amba_device spear300_gpio1_device;
/* pad mux modes */
extern struct pmx_mode spear300_nand_mode;
extern struct pmx_mode spear300_nor_mode;
extern struct pmx_mode spear300_photo_frame_mode;
extern struct pmx_mode spear300_lend_ip_phone_mode;
extern struct pmx_mode spear300_hend_ip_phone_mode;
extern struct pmx_mode spear300_lend_wifi_phone_mode;
extern struct pmx_mode spear300_hend_wifi_phone_mode;
extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
extern struct pmx_mode spear300_ata_pabx_i2s_mode;
extern struct pmx_mode spear300_caml_lcdw_mode;
extern struct pmx_mode spear300_camu_lcd_mode;
extern struct pmx_mode spear300_camu_wlcd_mode;
extern struct pmx_mode spear300_caml_lcd_mode;
/* pad mux devices */
extern struct pmx_dev spear300_pmx_fsmc_2_chips;
extern struct pmx_dev spear300_pmx_fsmc_4_chips;
extern struct pmx_dev spear300_pmx_keyboard;
extern struct pmx_dev spear300_pmx_clcd;
extern struct pmx_dev spear300_pmx_telecom_gpio;
extern struct pmx_dev spear300_pmx_telecom_tdm;
extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
extern struct pmx_dev spear300_pmx_telecom_camera;
extern struct pmx_dev spear300_pmx_telecom_dac;
extern struct pmx_dev spear300_pmx_telecom_i2s;
extern struct pmx_dev spear300_pmx_telecom_boot_pins;
extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
extern struct pmx_dev spear300_pmx_gpio1;
/* Add spear300 machine function declarations here */
void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR300 */
/* spear310 declarations */
#ifdef CONFIG_MACH_SPEAR310
/* Add spear310 machine device structure declarations here */
/* pad mux devices */
extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
extern struct pmx_dev spear310_pmx_emi_cs_2_3;
extern struct pmx_dev spear310_pmx_uart1;
extern struct pmx_dev spear310_pmx_uart2;
extern struct pmx_dev spear310_pmx_uart3_4_5;
extern struct pmx_dev spear310_pmx_fsmc;
extern struct pmx_dev spear310_pmx_rs485_0_1;
extern struct pmx_dev spear310_pmx_tdm0;
/* Add spear310 machine function declarations here */
void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR310 */
/* spear320 declarations */
#ifdef CONFIG_MACH_SPEAR320
/* Add spear320 machine device structure declarations here */
/* pad mux modes */
extern struct pmx_mode spear320_auto_net_smii_mode;
extern struct pmx_mode spear320_auto_net_mii_mode;
extern struct pmx_mode spear320_auto_exp_mode;
extern struct pmx_mode spear320_small_printers_mode;
/* pad mux devices */
extern struct pmx_dev spear320_pmx_clcd;
extern struct pmx_dev spear320_pmx_emi;
extern struct pmx_dev spear320_pmx_fsmc;
extern struct pmx_dev spear320_pmx_spp;
extern struct pmx_dev spear320_pmx_sdhci;
extern struct pmx_dev spear320_pmx_i2s;
extern struct pmx_dev spear320_pmx_uart1;
extern struct pmx_dev spear320_pmx_uart1_modem;
extern struct pmx_dev spear320_pmx_uart2;
extern struct pmx_dev spear320_pmx_touchscreen;
extern struct pmx_dev spear320_pmx_can;
extern struct pmx_dev spear320_pmx_sdhci_led;
extern struct pmx_dev spear320_pmx_pwm0;
extern struct pmx_dev spear320_pmx_pwm1;
extern struct pmx_dev spear320_pmx_pwm2;
extern struct pmx_dev spear320_pmx_pwm3;
extern struct pmx_dev spear320_pmx_ssp1;
extern struct pmx_dev spear320_pmx_ssp2;
extern struct pmx_dev spear320_pmx_mii1;
extern struct pmx_dev spear320_pmx_smii0;
extern struct pmx_dev spear320_pmx_smii1;
extern struct pmx_dev spear320_pmx_i2c1;
/* Add spear320 machine function declarations here */
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR320 */
#endif /* __MACH_GENERIC_H */
......@@ -17,7 +17,4 @@
#include <plat/hardware.h>
#include <mach/spear.h>
/* Vitual to physical translation of statically mapped space */
#define IO_ADDRESS(x) (x | 0xF0000000)
#endif /* __MACH_HARDWARE_H */
......@@ -25,8 +25,9 @@
/* ICM1 - Low speed connection */
#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
......@@ -53,11 +54,11 @@
#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
/* ICM3 - Basic Subsystem */
#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
......@@ -65,9 +66,9 @@
#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
/* Debug uart for linux, will be used for debug and uncompress messages */
......
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/*
* arch/arm/mach-spear3xx/spear300_evb.c
*
* SPEAr300 evaluation board source file
*
* Copyright (C) 2009 ST Microelectronics
* Viresh Kumar<viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/generic.h>
#include <mach/hardware.h>
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
&spear3xx_pmx_i2c,
&spear3xx_pmx_ssp_cs,
&spear3xx_pmx_ssp,
&spear3xx_pmx_mii,
&spear3xx_pmx_uart0,
/* spear300 specific devices */
&spear300_pmx_fsmc_2_chips,
&spear300_pmx_clcd,
&spear300_pmx_telecom_sdhci_4bit,
&spear300_pmx_gpio1,
};
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&spear3xx_gpio_device,
&spear3xx_uart_device,
/* spear300 specific devices */
&spear300_gpio1_device,
};
static struct platform_device *plat_devs[] __initdata = {
/* spear3xx specific devices */
/* spear300 specific devices */
};
static void __init spear300_evb_init(void)
{
unsigned int i;
/* call spear300 machine init function */
spear300_init(&spear300_photo_frame_mode, pmx_devs,
ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
/* Add Amba Devices */
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
amba_device_register(amba_devs[i], &iomem_resource);
}
MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
.atag_offset = 0x100,
.map_io = spear3xx_map_io,
.init_irq = spear3xx_init_irq,
.handle_irq = vic_handle_irq,
.timer = &spear3xx_timer,
.init_machine = spear300_evb_init,
.restart = spear_restart,
MACHINE_END
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