提交 cfd093bb 编写于 作者: J Joachim Eastwood 提交者: Kishon Vijay Abraham I

phy: lpc18xx-usb-otg: fix clock order in phy init

Changing the frequency of the USB clock must be done before the
PLL is powered on (prepared). This matters when the USB clock
is not setup by either boot ROM or boot loader. Reorder the
function calls to adhere to the order noted in the user manual.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
上级 4a9e5ca1
......@@ -33,12 +33,12 @@ static int lpc18xx_usb_otg_phy_init(struct phy *phy)
struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy);
int ret;
ret = clk_prepare(lpc->clk);
/* The PHY must be clocked at 480 MHz */
ret = clk_set_rate(lpc->clk, 480000000);
if (ret)
return ret;
/* The PHY must be clocked at 480 MHz */
return clk_set_rate(lpc->clk, 480000000);
return clk_prepare(lpc->clk);
}
static int lpc18xx_usb_otg_phy_exit(struct phy *phy)
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册