MIPS: Octeon: Make Octeon GPIO IRQ chip CPU hotplug-aware

Make Octeon GPIO IRQ chip CPU hotplug-aware

Seems that irq_cpu_offline callbacks were forgotten in v1 and v2 CIU
GPIO chips. There is such a callback for octeon_irq_chip_ciu2_gpio,
covering CIU2 chips. Without this callback GPIO IRQs are not being migrated
during core offlining. Patch is tested on Octeon II.
Signed-off-by: NAlexander Sverdlin <alexander.sverdlin@nsn.com>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8201/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

arch/mips/cavium-octeon/octeon-irq.c

@@ -809,6 +809,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
 	.irq_set_type = octeon_irq_ciu_gpio_set_type,
 #ifdef CONFIG_SMP
 	.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
+	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
 #endif
 	.flags = IRQCHIP_SET_TYPE_MASKED,
 };
@@ -823,6 +824,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = {
 	.irq_set_type = octeon_irq_ciu_gpio_set_type,
 #ifdef CONFIG_SMP
 	.irq_set_affinity = octeon_irq_ciu_set_affinity,
+	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
 #endif
 	.flags = IRQCHIP_SET_TYPE_MASKED,
 };