提交 ce105a08 编写于 作者: J John Dykstra 提交者: David S. Miller

pcnet32: Remove pointless memory barriers

These two memory barriers in performance-critical paths are not needed
on x86.  Even if some other architecture does buffer PCI I/O space
writes, the existing memory-mapped I/O barriers are unlikely to be what
is needed.
Signed-off-by: NJohn Dykstra <john.dykstra1@gmail.com>
Acked-by: NDon Fry <pcnet32@verizon.net>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
上级 dd4d8ca6
...@@ -1405,7 +1405,7 @@ static int pcnet32_poll(struct napi_struct *napi, int budget) ...@@ -1405,7 +1405,7 @@ static int pcnet32_poll(struct napi_struct *napi, int budget)
/* Set interrupt enable. */ /* Set interrupt enable. */
lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN); lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
mmiowb();
spin_unlock_irqrestore(&lp->lock, flags); spin_unlock_irqrestore(&lp->lock, flags);
} }
return work_done; return work_done;
...@@ -2597,7 +2597,7 @@ pcnet32_interrupt(int irq, void *dev_id) ...@@ -2597,7 +2597,7 @@ pcnet32_interrupt(int irq, void *dev_id)
val = lp->a.read_csr(ioaddr, CSR3); val = lp->a.read_csr(ioaddr, CSR3);
val |= 0x5f00; val |= 0x5f00;
lp->a.write_csr(ioaddr, CSR3, val); lp->a.write_csr(ioaddr, CSR3, val);
mmiowb();
__napi_schedule(&lp->napi); __napi_schedule(&lp->napi);
break; break;
} }
......
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