提交 cd9d1182 编写于 作者: E Ezequiel Garcia 提交者: David Woodhouse

mtd: nand: pxa3xx: Handle ECC and DMA enable/disable properly

When ECC is not selected, the ECC enable bit must be cleared
in the NAND control register. Same applies to DMA.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: NDaniel Mack <zonque@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
上级 c0f3b864
......@@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
uint32_t ndcr;
ndcr = host->reg_ndcr;
ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
if (info->use_ecc)
ndcr |= NDCR_ECC_EN;
else
ndcr &= ~NDCR_ECC_EN;
if (info->use_dma)
ndcr |= NDCR_DMA_EN;
else
ndcr &= ~NDCR_DMA_EN;
ndcr |= NDCR_ND_RUN;
/* clear status bits and run */
......
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