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提交 cc81d7f3 编写于 作者: J Jonas Gorski 提交者： Ralf Baechle
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MIPS: BCM63xx: Append irq line to irq_{stat,mask}* 

The SMP capable irq controllers have two interrupt output pins which are
controlled through separate registers, so make the variables arrays.
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Gregory Fong <gregory.0xf0@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7318/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 86ee4333
隐藏空白更改
内联 并排
Showing with 34 addition and 33 deletion
arch/mips/bcm63xx/irq.c
浏览文件 @ cc81d7f3
...@@ -19,7 +19,8 @@ ...@@ -19,7 +19,8 @@
#include <bcm63xx_io.h> #include <bcm63xx_io.h>
#include <bcm63xx_irq.h> #include <bcm63xx_irq.h>
static u32 irq_stat_addr, irq_mask_addr; static u32 irq_stat_addr[2];
static u32 irq_mask_addr[2];
static void (*dispatch_internal)(void); static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded; static int is_ext_irq_cascaded;
static unsigned int ext_irq_count; static unsigned int ext_irq_count;
...@@ -64,8 +65,8 @@ void __dispatch_internal_##width(void) \ ...@@ -64,8 +65,8 @@ void __dispatch_internal_##width(void) \
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
u32 val; \ u32 val; \
\ \
val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \ val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \ val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
pending[--tgt] = val; \ pending[--tgt] = val; \
\ \
if (val) \ if (val) \
...@@ -92,9 +93,9 @@ static void __internal_irq_mask_##width(unsigned int irq) \ ...@@ -92,9 +93,9 @@ static void __internal_irq_mask_##width(unsigned int irq) \
unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \ unsigned bit = irq & 0x1f; \
\ \
val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
val &= ~(1 << bit); \ val &= ~(1 << bit); \
bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
} \ } \
\ \
static void __internal_irq_unmask_##width(unsigned int irq) \ static void __internal_irq_unmask_##width(unsigned int irq) \
...@@ -103,9 +104,9 @@ static void __internal_irq_unmask_##width(unsigned int irq) \ ...@@ -103,9 +104,9 @@ static void __internal_irq_unmask_##width(unsigned int irq) \
unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \ unsigned bit = irq & 0x1f; \
\ \
val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
val |= (1 << bit); \ val |= (1 << bit); \
bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
} }
BUILD_IPIC_INTERNAL(32); BUILD_IPIC_INTERNAL(32);
...@@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void) ...@@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void)
{ {
int irq_bits; int irq_bits;
irq_stat_addr = bcm63xx_regset_address(RSET_PERF); irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
irq_mask_addr = bcm63xx_regset_address(RSET_PERF); irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) { switch (bcm63xx_get_cpu_id()) {
case BCM3368_CPU_ID: case BCM3368_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_3368_REG; irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
irq_mask_addr += PERF_IRQMASK_3368_REG; irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
irq_bits = 32; irq_bits = 32;
ext_irq_count = 4; ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
break; break;
case BCM6328_CPU_ID: case BCM6328_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6328_REG; irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
irq_mask_addr += PERF_IRQMASK_6328_REG; irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
irq_bits = 64; irq_bits = 64;
ext_irq_count = 4; ext_irq_count = 4;
is_ext_irq_cascaded = 1; is_ext_irq_cascaded = 1;
...@@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void) ...@@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
break; break;
case BCM6338_CPU_ID: case BCM6338_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6338_REG; irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
irq_mask_addr += PERF_IRQMASK_6338_REG; irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
irq_bits = 32; irq_bits = 32;
ext_irq_count = 4; ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
break; break;
case BCM6345_CPU_ID: case BCM6345_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6345_REG; irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
irq_mask_addr += PERF_IRQMASK_6345_REG; irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
irq_bits = 32; irq_bits = 32;
ext_irq_count = 4; ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
break; break;
case BCM6348_CPU_ID: case BCM6348_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6348_REG; irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
irq_mask_addr += PERF_IRQMASK_6348_REG; irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
irq_bits = 32; irq_bits = 32;
ext_irq_count = 4; ext_irq_count = 4;
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
break; break;
case BCM6358_CPU_ID: case BCM6358_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6358_REG; irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
irq_mask_addr += PERF_IRQMASK_6358_REG; irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
irq_bits = 32; irq_bits = 32;
ext_irq_count = 4; ext_irq_count = 4;
is_ext_irq_cascaded = 1; is_ext_irq_cascaded = 1;
...@@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void) ...@@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
break; break;
case BCM6362_CPU_ID: case BCM6362_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6362_REG; irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
irq_mask_addr += PERF_IRQMASK_6362_REG; irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
irq_bits = 64; irq_bits = 64;
ext_irq_count = 4; ext_irq_count = 4;
is_ext_irq_cascaded = 1; is_ext_irq_cascaded = 1;
...@@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void) ...@@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
break; break;
case BCM6368_CPU_ID: case BCM6368_CPU_ID:
irq_stat_addr += PERF_IRQSTAT_6368_REG; irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
irq_mask_addr += PERF_IRQMASK_6368_REG; irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
irq_bits = 64; irq_bits = 64;
ext_irq_count = 6; ext_irq_count = 6;
is_ext_irq_cascaded = 1; is_ext_irq_cascaded = 1;
......
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
浏览文件 @ cc81d7f3
...@@ -215,23 +215,23 @@ ...@@ -215,23 +215,23 @@
/* Interrupt Mask register */ /* Interrupt Mask register */
#define PERF_IRQMASK_3368_REG 0xc #define PERF_IRQMASK_3368_REG 0xc
#define PERF_IRQMASK_6328_REG 0x20 #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
#define PERF_IRQMASK_6338_REG 0xc #define PERF_IRQMASK_6338_REG 0xc
#define PERF_IRQMASK_6345_REG 0xc #define PERF_IRQMASK_6345_REG 0xc
#define PERF_IRQMASK_6348_REG 0xc #define PERF_IRQMASK_6348_REG 0xc
#define PERF_IRQMASK_6358_REG 0xc #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
#define PERF_IRQMASK_6362_REG 0x20 #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
#define PERF_IRQMASK_6368_REG 0x20 #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
/* Interrupt Status register */ /* Interrupt Status register */
#define PERF_IRQSTAT_3368_REG 0x10 #define PERF_IRQSTAT_3368_REG 0x10
#define PERF_IRQSTAT_6328_REG 0x28 #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
#define PERF_IRQSTAT_6338_REG 0x10 #define PERF_IRQSTAT_6338_REG 0x10
#define PERF_IRQSTAT_6345_REG 0x10 #define PERF_IRQSTAT_6345_REG 0x10
#define PERF_IRQSTAT_6348_REG 0x10 #define PERF_IRQSTAT_6348_REG 0x10
#define PERF_IRQSTAT_6358_REG 0x10 #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
#define PERF_IRQSTAT_6362_REG 0x28 #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
#define PERF_IRQSTAT_6368_REG 0x28 #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
/* External Interrupt Configuration register */ /* External Interrupt Configuration register */
#define PERF_EXTIRQ_CFG_REG_3368 0x14 #define PERF_EXTIRQ_CFG_REG_3368 0x14
......
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