Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openanolis
cloud-kernel
提交
caa1d631
cloud-kernel
项目概览
openanolis
/
cloud-kernel
大约 1 年 前同步成功
通知
158
Star
36
Fork
7
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
10
列表
看板
标记
里程碑
合并请求
2
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
cloud-kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
10
Issue
10
列表
看板
标记
里程碑
合并请求
2
合并请求
2
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
caa1d631
编写于
9月 18, 2012
作者:
B
Benjamin Herrenschmidt
浏览文件
操作
浏览文件
下载
差异文件
Merge remote-tracking branch 'kumar/next' into next
上级
1e38b714
905e75c4
变更
101
展开全部
隐藏空白更改
内联
并排
Showing
101 changed file
with
2421 addition
and
1024 deletion
+2421
-1024
Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
+6
-3
arch/powerpc/Kconfig
arch/powerpc/Kconfig
+4
-2
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
+58
-0
arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
+52
-0
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
+59
-0
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+3
-0
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+320
-0
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+114
-0
arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
+118
-0
arch/powerpc/boot/dts/mpc8536ds.dtsi
arch/powerpc/boot/dts/mpc8536ds.dtsi
+4
-0
arch/powerpc/boot/dts/mpc8540ads.dts
arch/powerpc/boot/dts/mpc8540ads.dts
+2
-0
arch/powerpc/boot/dts/mpc8541cds.dts
arch/powerpc/boot/dts/mpc8541cds.dts
+2
-0
arch/powerpc/boot/dts/mpc8544ds.dts
arch/powerpc/boot/dts/mpc8544ds.dts
+3
-1
arch/powerpc/boot/dts/mpc8544ds.dtsi
arch/powerpc/boot/dts/mpc8544ds.dtsi
+39
-0
arch/powerpc/boot/dts/mpc8555cds.dts
arch/powerpc/boot/dts/mpc8555cds.dts
+2
-0
arch/powerpc/boot/dts/mpc8560ads.dts
arch/powerpc/boot/dts/mpc8560ads.dts
+2
-0
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
+0
-63
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
+0
-141
arch/powerpc/boot/dts/p1022ds.dtsi
arch/powerpc/boot/dts/p1022ds.dtsi
+4
-0
arch/powerpc/boot/dts/p1022rdk.dts
arch/powerpc/boot/dts/p1022rdk.dts
+188
-0
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+0
-67
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+0
-125
arch/powerpc/boot/dts/p2041rdb.dts
arch/powerpc/boot/dts/p2041rdb.dts
+4
-0
arch/powerpc/boot/dts/p3041ds.dts
arch/powerpc/boot/dts/p3041ds.dts
+4
-0
arch/powerpc/boot/dts/p4080ds.dts
arch/powerpc/boot/dts/p4080ds.dts
+4
-0
arch/powerpc/boot/dts/p5020ds.dts
arch/powerpc/boot/dts/p5020ds.dts
+4
-0
arch/powerpc/boot/dts/p5040ds.dts
arch/powerpc/boot/dts/p5040ds.dts
+207
-0
arch/powerpc/configs/corenet32_smp_defconfig
arch/powerpc/configs/corenet32_smp_defconfig
+1
-0
arch/powerpc/configs/corenet64_smp_defconfig
arch/powerpc/configs/corenet64_smp_defconfig
+1
-0
arch/powerpc/configs/mpc85xx_defconfig
arch/powerpc/configs/mpc85xx_defconfig
+1
-0
arch/powerpc/configs/mpc85xx_smp_defconfig
arch/powerpc/configs/mpc85xx_smp_defconfig
+1
-0
arch/powerpc/include/asm/cacheflush.h
arch/powerpc/include/asm/cacheflush.h
+2
-0
arch/powerpc/include/asm/fsl_guts.h
arch/powerpc/include/asm/fsl_guts.h
+2
-0
arch/powerpc/include/asm/fsl_ifc.h
arch/powerpc/include/asm/fsl_ifc.h
+8
-6
arch/powerpc/include/asm/mpic.h
arch/powerpc/include/asm/mpic.h
+19
-0
arch/powerpc/include/asm/smp.h
arch/powerpc/include/asm/smp.h
+2
-0
arch/powerpc/include/asm/swiotlb.h
arch/powerpc/include/asm/swiotlb.h
+6
-0
arch/powerpc/kernel/cpu_setup_fsl_booke.S
arch/powerpc/kernel/cpu_setup_fsl_booke.S
+65
-9
arch/powerpc/kernel/cputable.c
arch/powerpc/kernel/cputable.c
+4
-0
arch/powerpc/kernel/dma-swiotlb.c
arch/powerpc/kernel/dma-swiotlb.c
+20
-0
arch/powerpc/kernel/exceptions-64e.S
arch/powerpc/kernel/exceptions-64e.S
+2
-16
arch/powerpc/kernel/head_fsl_booke.S
arch/powerpc/kernel/head_fsl_booke.S
+32
-14
arch/powerpc/kernel/smp.c
arch/powerpc/kernel/smp.c
+11
-1
arch/powerpc/mm/mem.c
arch/powerpc/mm/mem.c
+1
-2
arch/powerpc/platforms/44x/currituck.c
arch/powerpc/platforms/44x/currituck.c
+2
-8
arch/powerpc/platforms/85xx/Kconfig
arch/powerpc/platforms/85xx/Kconfig
+21
-0
arch/powerpc/platforms/85xx/Makefile
arch/powerpc/platforms/85xx/Makefile
+2
-0
arch/powerpc/platforms/85xx/common.c
arch/powerpc/platforms/85xx/common.c
+10
-0
arch/powerpc/platforms/85xx/corenet_ds.c
arch/powerpc/platforms/85xx/corenet_ds.c
+11
-27
arch/powerpc/platforms/85xx/ge_imp3a.c
arch/powerpc/platforms/85xx/ge_imp3a.c
+20
-42
arch/powerpc/platforms/85xx/mpc8536_ds.c
arch/powerpc/platforms/85xx/mpc8536_ds.c
+3
-33
arch/powerpc/platforms/85xx/mpc85xx_ads.c
arch/powerpc/platforms/85xx/mpc85xx_ads.c
+3
-8
arch/powerpc/platforms/85xx/mpc85xx_cds.c
arch/powerpc/platforms/85xx/mpc85xx_cds.c
+31
-13
arch/powerpc/platforms/85xx/mpc85xx_ds.c
arch/powerpc/platforms/85xx/mpc85xx_ds.c
+7
-8
arch/powerpc/platforms/85xx/mpc85xx_mds.c
arch/powerpc/platforms/85xx/mpc85xx_mds.c
+6
-34
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+12
-18
arch/powerpc/platforms/85xx/p1010rdb.c
arch/powerpc/platforms/85xx/p1010rdb.c
+2
-12
arch/powerpc/platforms/85xx/p1022_ds.c
arch/powerpc/platforms/85xx/p1022_ds.c
+4
-32
arch/powerpc/platforms/85xx/p1022_rdk.c
arch/powerpc/platforms/85xx/p1022_rdk.c
+167
-0
arch/powerpc/platforms/85xx/p1023_rds.c
arch/powerpc/platforms/85xx/p1023_rds.c
+3
-6
arch/powerpc/platforms/85xx/p2041_rdb.c
arch/powerpc/platforms/85xx/p2041_rdb.c
+1
-1
arch/powerpc/platforms/85xx/p3041_ds.c
arch/powerpc/platforms/85xx/p3041_ds.c
+1
-1
arch/powerpc/platforms/85xx/p4080_ds.c
arch/powerpc/platforms/85xx/p4080_ds.c
+1
-1
arch/powerpc/platforms/85xx/p5020_ds.c
arch/powerpc/platforms/85xx/p5020_ds.c
+1
-1
arch/powerpc/platforms/85xx/p5040_ds.c
arch/powerpc/platforms/85xx/p5040_ds.c
+89
-0
arch/powerpc/platforms/85xx/qemu_e500.c
arch/powerpc/platforms/85xx/qemu_e500.c
+3
-2
arch/powerpc/platforms/85xx/sbc8548.c
arch/powerpc/platforms/85xx/sbc8548.c
+3
-18
arch/powerpc/platforms/85xx/smp.c
arch/powerpc/platforms/85xx/smp.c
+183
-37
arch/powerpc/platforms/85xx/socrates.c
arch/powerpc/platforms/85xx/socrates.c
+2
-9
arch/powerpc/platforms/85xx/stx_gp3.c
arch/powerpc/platforms/85xx/stx_gp3.c
+3
-10
arch/powerpc/platforms/85xx/tqm85xx.c
arch/powerpc/platforms/85xx/tqm85xx.c
+2
-19
arch/powerpc/platforms/85xx/xes_mpc85xx.c
arch/powerpc/platforms/85xx/xes_mpc85xx.c
+8
-48
arch/powerpc/platforms/86xx/gef_ppc9a.c
arch/powerpc/platforms/86xx/gef_ppc9a.c
+4
-8
arch/powerpc/platforms/86xx/gef_sbc310.c
arch/powerpc/platforms/86xx/gef_sbc310.c
+4
-9
arch/powerpc/platforms/86xx/gef_sbc610.c
arch/powerpc/platforms/86xx/gef_sbc610.c
+4
-8
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+6
-15
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+6
-36
arch/powerpc/platforms/86xx/sbc8641d.c
arch/powerpc/platforms/86xx/sbc8641d.c
+4
-10
arch/powerpc/sysdev/Makefile
arch/powerpc/sysdev/Makefile
+1
-1
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+10
-0
arch/powerpc/sysdev/fsl_mpic_err.c
arch/powerpc/sysdev/fsl_mpic_err.c
+149
-0
arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pci.c
+71
-47
arch/powerpc/sysdev/fsl_pci.h
arch/powerpc/sysdev/fsl_pci.h
+16
-4
arch/powerpc/sysdev/mpic.c
arch/powerpc/sysdev/mpic.c
+85
-17
arch/powerpc/sysdev/mpic.h
arch/powerpc/sysdev/mpic.h
+22
-0
drivers/edac/mpc85xx_edac.c
drivers/edac/mpc85xx_edac.c
+12
-31
未找到文件。
Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
浏览文件 @
caa1d631
...
...
@@ -12,9 +12,12 @@ Properties:
- #size-cells : Either one or two, depending on how large each chipselect
can be.
- reg : Offset and length of the register set for the device
- interrupts : IFC has two interrupts. The first one is the "common"
interrupt(CM_EVTER_STAT), and second is the NAND interrupt
(NAND_EVTER_STAT).
- interrupts: IFC may have one or two interrupts. If two interrupt
specifiers are present, the first is the "common"
interrupt (CM_EVTER_STAT), and the second is the NAND
interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
- ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
...
...
arch/powerpc/Kconfig
浏览文件 @
caa1d631
...
...
@@ -215,7 +215,8 @@ config ARCH_HIBERNATION_POSSIBLE
config ARCH_SUSPEND_POSSIBLE
def_bool y
depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
(PPC_85xx && !SMP) || PPC_86xx || PPC_PSERIES || 44x || 40x
(PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \
|| 44x || 40x
config PPC_DCR_NATIVE
bool
...
...
@@ -328,7 +329,8 @@ config SWIOTLB
config HOTPLUG_CPU
bool "Support for enabling/disabling CPUs"
depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || PPC_PMAC || PPC_POWERNV)
depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || \
PPC_PMAC || PPC_POWERNV || (PPC_85xx && !PPC_E500MC))
---help---
Say Y here to be able to disable and re-enable individual
CPUs at runtime on SMP machines.
...
...
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
0 → 100644
浏览文件 @
caa1d631
/*
* e500mc Power ISA Device Tree Source (include)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/ {
cpus {
power-isa-version = "2.06";
power-isa-b; // Base
power-isa-e; // Embedded
power-isa-atb; // Alternate Time Base
power-isa-cs; // Cache Specification
power-isa-ds; // Decorated Storage
power-isa-e.ed; // Embedded.Enhanced Debug
power-isa-e.pd; // Embedded.External PID
power-isa-e.hv; // Embedded.Hypervisor
power-isa-e.le; // Embedded.Little-Endian
power-isa-e.pm; // Embedded.Performance Monitor
power-isa-e.pc; // Embedded.Processor Control
power-isa-ecl; // Embedded Cache Locking
power-isa-exp; // External Proxy
power-isa-fp; // Floating Point
power-isa-fp.r; // Floating Point.Record
power-isa-mmc; // Memory Coherence
power-isa-scpm; // Store Conditional Page Mobility
power-isa-wt; // Wait
mmu-type = "power-embedded";
};
};
arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
0 → 100644
浏览文件 @
caa1d631
/*
* e500v2 Power ISA Device Tree Source (include)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/ {
cpus {
power-isa-version = "2.03";
power-isa-b; // Base
power-isa-e; // Embedded
power-isa-atb; // Alternate Time Base
power-isa-cs; // Cache Specification
power-isa-e.le; // Embedded.Little-Endian
power-isa-e.pm; // Embedded.Performance Monitor
power-isa-ecl; // Embedded Cache Locking
power-isa-mmc; // Memory Coherence
power-isa-sp; // Signal Processing Engine
power-isa-sp.fd; // SPE.Embedded Float Scalar Double
power-isa-sp.fs; // SPE.Embedded Float Scalar Single
power-isa-sp.fv; // SPE.Embedded Float Vector
mmu-type = "power-embedded";
};
};
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
0 → 100644
浏览文件 @
caa1d631
/*
* e5500 Power ISA Device Tree Source (include)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/ {
cpus {
power-isa-version = "2.06";
power-isa-b; // Base
power-isa-e; // Embedded
power-isa-atb; // Alternate Time Base
power-isa-cs; // Cache Specification
power-isa-ds; // Decorated Storage
power-isa-e.ed; // Embedded.Enhanced Debug
power-isa-e.pd; // Embedded.External PID
power-isa-e.hv; // Embedded.Hypervisor
power-isa-e.le; // Embedded.Little-Endian
power-isa-e.pm; // Embedded.Performance Monitor
power-isa-e.pc; // Embedded.Processor Control
power-isa-ecl; // Embedded Cache Locking
power-isa-exp; // External Proxy
power-isa-fp; // Floating Point
power-isa-fp.r; // Floating Point.Record
power-isa-mmc; // Memory Coherence
power-isa-scpm; // Store Conditional Page Mobility
power-isa-wt; // Wait
power-isa-64; // 64-bit
mmu-type = "power-embedded";
};
};
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,MPC8536";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,MPC8544";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,MPC8548";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,MPC8568";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,MPC8569";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,MPC8572";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P1010";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P1020";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P1021";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P1022";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P1023";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P2020";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500mc_power_isa.dtsi"
/ {
compatible = "fsl,P2041";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500mc_power_isa.dtsi"
/ {
compatible = "fsl,P3041";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e500mc_power_isa.dtsi"
/ {
compatible = "fsl,P4080";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
浏览文件 @
caa1d631
...
...
@@ -33,6 +33,9 @@
*/
/dts-v1/;
/include/ "e5500_power_isa.dtsi"
/ {
compatible = "fsl,P5020";
#address-cells = <2>;
...
...
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
0 → 100644
浏览文件 @
caa1d631
/*
* P5040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* This software is provided by Freescale Semiconductor "as is" and any
* express or implied warranties, including, but not limited to, the implied
* warranties of merchantability and fitness for a particular purpose are
* disclaimed. In no event shall Freescale Semiconductor be liable for any
* direct, indirect, incidental, special, exemplary, or consequential damages
* (including, but not limited to, procurement of substitute goods or services;
* loss of use, data, or profits; or business interruption) however caused and
* on any theory of liability, whether in contract, strict liability, or tort
* (including negligence or otherwise) arising in any way out of the use of this
* software, even if advised of the possibility of such damage.
*/
&lbc {
compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
#address-cells = <2>;
#size-cells = <1>;
};
/* controller at 0x200000 */
&pci0 {
compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <33333333>;
interrupts = <16 2 1 15>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <16 2 1 15>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 40 1 0 0
0000 0 0 2 &mpic 1 1 0 0
0000 0 0 3 &mpic 2 1 0 0
0000 0 0 4 &mpic 3 1 0 0
>;
};
};
/* controller at 0x201000 */
&pci1 {
compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0 0xff>;
clock-frequency = <33333333>;
interrupts = <16 2 1 14>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <16 2 1 14>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 41 1 0 0
0000 0 0 2 &mpic 5 1 0 0
0000 0 0 3 &mpic 6 1 0 0
0000 0 0 4 &mpic 7 1 0 0
>;
};
};
/* controller at 0x202000 */
&pci2 {
compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <33333333>;
interrupts = <16 2 1 13>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <16 2 1 13>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 42 1 0 0
0000 0 0 2 &mpic 9 1 0 0
0000 0 0 3 &mpic 10 1 0 0
0000 0 0 4 &mpic 11 1 0 0
>;
};
};
&dcsr {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,dcsr", "simple-bus";
dcsr-epu@0 {
compatible = "fsl,dcsr-epu";
interrupts = <52 2 0 0
84 2 0 0
85 2 0 0>;
reg = <0x0 0x1000>;
};
dcsr-npc {
compatible = "fsl,dcsr-npc";
reg = <0x1000 0x1000 0x1000000 0x8000>;
};
dcsr-nxc@2000 {
compatible = "fsl,dcsr-nxc";
reg = <0x2000 0x1000>;
};
dcsr-corenet {
compatible = "fsl,dcsr-corenet";
reg = <0x8000 0x1000 0xB0000 0x1000>;
};
dcsr-dpaa@9000 {
compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
reg = <0x9000 0x1000>;
};
dcsr-ocn@11000 {
compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
reg = <0x11000 0x1000>;
};
dcsr-ddr@12000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr1>;
reg = <0x12000 0x1000>;
};
dcsr-ddr@13000 {
compatible = "fsl,dcsr-ddr";
dev-handle = <&ddr2>;
reg = <0x13000 0x1000>;
};
dcsr-nal@18000 {
compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
reg = <0x18000 0x1000>;
};
dcsr-rcpm@22000 {
compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
reg = <0x22000 0x1000>;
};
dcsr-cpu-sb-proxy@40000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu0>;
reg = <0x40000 0x1000>;
};
dcsr-cpu-sb-proxy@41000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu1>;
reg = <0x41000 0x1000>;
};
dcsr-cpu-sb-proxy@42000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu2>;
reg = <0x42000 0x1000>;
};
dcsr-cpu-sb-proxy@43000 {
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
cpu-handle = <&cpu3>;
reg = <0x43000 0x1000>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
soc-sram-error {
compatible = "fsl,soc-sram-error";
interrupts = <16 2 1 29>;
};
corenet-law@0 {
compatible = "fsl,corenet-law";
reg = <0x0 0x1000>;
fsl,num-laws = <32>;
};
ddr1: memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
ddr2: memory-controller@9000 {
compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
reg = <0x9000 0x1000>;
interrupts = <16 2 1 22>;
};
cpc: l3-cache-controller@10000 {
compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
reg = <0x10000 0x1000
0x11000 0x1000>;
interrupts = <16 2 1 27
16 2 1 26>;
};
corenet-cf@18000 {
compatible = "fsl,corenet-cf";
reg = <0x18000 0x1000>;
interrupts = <16 2 1 31>;
fsl,ccf-num-csdids = <32>;
fsl,ccf-num-snoopids = <32>;
};
iommu@20000 {
compatible = "fsl,pamu-v1.0", "fsl,pamu";
reg = <0x20000 0x5000>;
interrupts = <
24 2 0 0
16 2 1 30>;
};
/include/ "qoriq-mpic.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0";
reg = <0xe0000 0xe00>;
fsl,has-rstcr;
#sleep-cells = <1>;
fsl,liodn-bits = <12>;
};
pins: global-utilities@e0e00 {
compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0";
reg = <0xe0e00 0x200>;
#sleep-cells = <2>;
};
clockgen: global-utilities@e1000 {
compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
};
rcpm: global-utilities@e2000 {
compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0";
reg = <0xe2000 0x1000>;
#sleep-cells = <1>;
};
sfp: sfp@e8000 {
compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
reg = <0xe8000 0x1000>;
};
serdes: serdes@ea000 {
compatible = "fsl,p5040-serdes";
reg = <0xea000 0x1000>;
};
/include/ "qoriq-dma-0.dtsi"
/include/ "qoriq-dma-1.dtsi"
/include/ "qoriq-espi-0.dtsi"
spi@110000 {
fsl,espi-num-chipselects = <4>;
};
/include/ "qoriq-esdhc-0.dtsi"
sdhc@114000 {
sdhci,auto-cmd12;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi"
usb0: usb@210000 {
compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
phy_type = "utmi";
port0;
};
/include/ "qoriq-usb2-dr-0.dtsi"
usb1: usb@211000 {
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
dr_mode = "host";
phy_type = "utmi";
};
/include/ "qoriq-sata2-0.dtsi"
/include/ "qoriq-sata2-1.dtsi"
/include/ "qoriq-sec5.2-0.dtsi"
};
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
0 → 100644
浏览文件 @
caa1d631
/*
* P5040 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* This software is provided by Freescale Semiconductor "as is" and any
* express or implied warranties, including, but not limited to, the implied
* warranties of merchantability and fitness for a particular purpose are
* disclaimed. In no event shall Freescale Semiconductor be liable for any
* direct, indirect, incidental, special, exemplary, or consequential damages
* (including, but not limited to, procurement of substitute goods or services;
* loss of use, data, or profits; or business interruption) however caused and
* on any theory of liability, whether in contract, strict liability, or tort
* (including negligence or otherwise) arising in any way out of the use of this
* software, even if advised of the possibility of such damage.
*/
/dts-v1/;
/include/ "e5500_power_isa.dtsi"
/ {
compatible = "fsl,P5040";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
ccsr = &soc;
dcsr = &dcsr;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
usb0 = &usb0;
usb1 = &usb1;
dma0 = &dma0;
dma1 = &dma1;
sdhc = &sdhc;
msi0 = &msi0;
msi1 = &msi1;
msi2 = &msi2;
crypto = &crypto;
sec_jr0 = &sec_jr0;
sec_jr1 = &sec_jr1;
sec_jr2 = &sec_jr2;
sec_jr3 = &sec_jr3;
rtic_a = &rtic_a;
rtic_b = &rtic_b;
rtic_c = &rtic_c;
rtic_d = &rtic_d;
sec_mon = &sec_mon;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu2: PowerPC,e5500@2 {
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
};
cpu3: PowerPC,e5500@3 {
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
0 → 100644
浏览文件 @
caa1d631
/*
* QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
crypto: crypto@300000 {
compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupts = <92 2 0 0>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <88 2 0 0>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <89 2 0 0>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <90 2 0 0>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <91 2 0 0>;
};
rtic@6000 {
compatible = "fsl,sec-v5.2-rtic",
"fsl,sec-v5.0-rtic",
"fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v5.2-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v5.2-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v5.2-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v5.2-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupts = <93 2 0 0>;
};
arch/powerpc/boot/dts/mpc8536ds.dtsi
浏览文件 @
caa1d631
...
...
@@ -132,6 +132,10 @@
reg = <0x68>;
interrupts = <0 0x1 0 0>;
};
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
spi@7000 {
...
...
arch/powerpc/boot/dts/mpc8540ads.dts
浏览文件 @
caa1d631
...
...
@@ -11,6 +11,8 @@
/
dts
-
v1
/;
/
include
/
"fsl/e500v2_power_isa.dtsi"
/
{
model
=
"MPC8540ADS"
;
compatible
=
"MPC8540ADS"
,
"MPC85xxADS"
;
...
...
arch/powerpc/boot/dts/mpc8541cds.dts
浏览文件 @
caa1d631
...
...
@@ -11,6 +11,8 @@
/
dts
-
v1
/;
/
include
/
"fsl/e500v2_power_isa.dtsi"
/
{
model
=
"MPC8541CDS"
;
compatible
=
"MPC8541CDS"
,
"MPC85xxCDS"
;
...
...
arch/powerpc/boot/dts/mpc8544ds.dts
浏览文件 @
caa1d631
...
...
@@ -20,8 +20,10 @@
reg
=
<
0
0
0
0
>;
//
Filled
by
U
-
Boot
};
lbc
:
localbus
@
e0005000
{
board_lbc
:
lbc
:
localbus
@
e0005000
{
reg
=
<
0
0xe0005000
0
0x1000
>;
ranges
=
<
0x0
0x0
0x0
0xff800000
0x800000
>;
};
board_soc
:
soc
:
soc8544
@
e0000000
{
...
...
arch/powerpc/boot/dts/mpc8544ds.dtsi
浏览文件 @
caa1d631
...
...
@@ -32,6 +32,45 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&board_lbc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
reg = <0x0 0x10000>;
label = "dtb-nor";
};
partition@20000 {
reg = <0x20000 0x30000>;
label = "diagnostic-nor";
read-only;
};
partition@200000 {
reg = <0x200000 0x200000>;
label = "dink-nor";
read-only;
};
partition@400000 {
reg = <0x400000 0x380000>;
label = "kernel-nor";
};
partition@780000 {
reg = <0x780000 0x80000>;
label = "u-boot-nor";
read-only;
};
};
};
&board_soc {
enet0: ethernet@24000 {
phy-handle = <&phy0>;
...
...
arch/powerpc/boot/dts/mpc8555cds.dts
浏览文件 @
caa1d631
...
...
@@ -11,6 +11,8 @@
/
dts
-
v1
/;
/
include
/
"fsl/e500v2_power_isa.dtsi"
/
{
model
=
"MPC8555CDS"
;
compatible
=
"MPC8555CDS"
,
"MPC85xxCDS"
;
...
...
arch/powerpc/boot/dts/mpc8560ads.dts
浏览文件 @
caa1d631
...
...
@@ -11,6 +11,8 @@
/
dts
-
v1
/;
/
include
/
"fsl/e500v2_power_isa.dtsi"
/
{
model
=
"MPC8560ADS"
;
compatible
=
"MPC8560ADS"
,
"MPC85xxADS"
;
...
...
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
已删除
100644 → 0
浏览文件 @
1e38b714
/*
*
P1020
RDB
Core0
Device
Tree
Source
in
CAMP
mode
.
*
*
In
CAMP
mode
,
each
core
needs
to
have
its
own
dts
.
Only
mpic
and
L2
cache
*
can
be
shared
,
all
the
other
devices
must
be
assigned
to
one
core
only
.
*
This
dts
file
allows
core0
to
have
memory
,
l2
,
i2c
,
spi
,
gpio
,
tdm
,
dma
,
usb
,
*
eth1
,
eth2
,
sdhc
,
crypto
,
global
-
util
,
message
,
pci0
,
pci1
,
msi
.
*
*
Please
note
to
add
"-b 0"
for
core0
's dts compiling.
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "p1020rdb.dts"
/ {
model = "fsl,P1020RDB";
compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
aliases {
ethernet1 = &enet1;
ethernet2 = &enet2;
serial0 = &serial0;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
PowerPC,P1020@1 {
status = "disabled";
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
serial1: serial@4600 {
status = "disabled";
};
enet0: ethernet@b0000 {
status = "disabled";
};
mpic: pic@40000 {
protected-sources = <
42 29 30 34 /* serial1, enet0-queue-group0 */
17 18 24 45 /* enet0-queue-group1, crypto */
>;
};
};
};
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
已删除
100644 → 0
浏览文件 @
1e38b714
/*
*
P1020
RDB
Core1
Device
Tree
Source
in
CAMP
mode
.
*
*
In
CAMP
mode
,
each
core
needs
to
have
its
own
dts
.
Only
mpic
and
L2
cache
*
can
be
shared
,
all
the
other
devices
must
be
assigned
to
one
core
only
.
*
This
dts
allows
core1
to
have
l2
,
eth0
,
crypto
.
*
*
Please
note
to
add
"-b 1"
for
core1
's dts compiling.
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "p1020rdb.dts"
/ {
model = "fsl,P1020RDB";
compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
aliases {
ethernet0 = &enet0;
serial0 = &serial1;
};
cpus {
PowerPC,P1020@0 {
status = "disabled";
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
ecm-law@0 {
status = "disabled";
};
ecm@1000 {
status = "disabled";
};
memory-controller@2000 {
status = "disabled";
};
i2c@3000 {
status = "disabled";
};
i2c@3100 {
status = "disabled";
};
serial0: serial@4500 {
status = "disabled";
};
spi@7000 {
status = "disabled";
};
gpio: gpio-controller@f000 {
status = "disabled";
};
dma@21300 {
status = "disabled";
};
mdio@24000 {
status = "disabled";
};
mdio@25000 {
status = "disabled";
};
enet1: ethernet@b1000 {
status = "disabled";
};
enet2: ethernet@b2000 {
status = "disabled";
};
usb@22000 {
status = "disabled";
};
sdhci@2e000 {
status = "disabled";
};
mpic: pic@40000 {
protected-sources = <
16 /* ecm, mem, L2, pci0, pci1 */
43 42 59 /* i2c, serial0, spi */
47 63 62 /* gpio, tdm */
20 21 22 23 /* dma */
03 02 /* mdio */
35 36 40 /* enet1-queue-group0 */
51 52 67 /* enet1-queue-group1 */
31 32 33 /* enet2-queue-group0 */
25 26 27 /* enet2-queue-group1 */
28 72 58 /* usb, sdhci, crypto */
0xb0 0xb1 0xb2 /* message */
0xb3 0xb4 0xb5
0xb6 0xb7
0xe0 0xe1 0xe2 /* msi */
0xe3 0xe4 0xe5
0xe6 0xe7 /* sdhci, crypto , pci */
>;
};
msi@41600 {
status = "disabled";
};
global-utilities@e0000 { //global utilities block
status = "disabled";
};
};
pci0: pcie@ffe09000 {
status = "disabled";
};
pci1: pcie@ffe0a000 {
status = "disabled";
};
};
arch/powerpc/boot/dts/p1022ds.dtsi
浏览文件 @
caa1d631
...
...
@@ -149,6 +149,10 @@
compatible = "dallas,ds1339";
reg = <0x68>;
};
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
spi@7000 {
...
...
arch/powerpc/boot/dts/p1022rdk.dts
0 → 100644
浏览文件 @
caa1d631
/*
*
P1022
RDK
32
-
bit
Physical
Address
Map
Device
Tree
Source
*
*
Copyright
2012
Freescale
Semiconductor
Inc
.
*
*
Redistribution
and
use
in
source
and
binary
forms
,
with
or
without
*
modification
,
are
permitted
provided
that
the
following
conditions
are
met
:
*
*
Redistributions
of
source
code
must
retain
the
above
copyright
*
notice
,
this
list
of
conditions
and
the
following
disclaimer
.
*
*
Redistributions
in
binary
form
must
reproduce
the
above
copyright
*
notice
,
this
list
of
conditions
and
the
following
disclaimer
in
the
*
documentation
and
/
or
other
materials
provided
with
the
distribution
.
*
*
Neither
the
name
of
Freescale
Semiconductor
nor
the
*
names
of
its
contributors
may
be
used
to
endorse
or
promote
products
*
derived
from
this
software
without
specific
prior
written
permission
.
*
*
*
ALTERNATIVELY
,
this
software
may
be
distributed
under
the
terms
of
the
*
GNU
General
Public
License
(
"GPL"
)
as
published
by
the
Free
Software
*
Foundation
,
either
version
2
of
that
License
or
(
at
your
option
)
any
*
later
version
.
*
*
THIS
SOFTWARE
IS
PROVIDED
BY
Freescale
Semiconductor
"AS IS"
AND
ANY
*
EXPRESS
OR
IMPLIED
WARRANTIES
,
INCLUDING
,
BUT
NOT
LIMITED
TO
,
THE
IMPLIED
*
WARRANTIES
OF
MERCHANTABILITY
AND
FITNESS
FOR
A
PARTICULAR
PURPOSE
ARE
*
DISCLAIMED
.
IN
NO
EVENT
SHALL
Freescale
Semiconductor
BE
LIABLE
FOR
ANY
*
DIRECT
,
INDIRECT
,
INCIDENTAL
,
SPECIAL
,
EXEMPLARY
,
OR
CONSEQUENTIAL
DAMAGES
*
(
INCLUDING
,
BUT
NOT
LIMITED
TO
,
PROCUREMENT
OF
SUBSTITUTE
GOODS
OR
SERVICES
;
*
LOSS
OF
USE
,
DATA
,
OR
PROFITS
;
OR
BUSINESS
INTERRUPTION
)
HOWEVER
CAUSED
AND
*
ON
ANY
THEORY
OF
LIABILITY
,
WHETHER
IN
CONTRACT
,
STRICT
LIABILITY
,
OR
TORT
*
(
INCLUDING
NEGLIGENCE
OR
OTHERWISE
)
ARISING
IN
ANY
WAY
OUT
OF
THE
USE
OF
THIS
*
SOFTWARE
,
EVEN
IF
ADVISED
OF
THE
POSSIBILITY
OF
SUCH
DAMAGE
.
*/
/
include
/
"fsl/p1022si-pre.dtsi"
/
{
model
=
"fsl,P1022RDK"
;
compatible
=
"fsl,P1022RDK"
;
memory
{
device_type
=
"memory"
;
};
board_lbc
:
lbc
:
localbus
@
ffe05000
{
/*
The
P1022
RDK
does
not
have
any
localbus
devices
*/
status
=
"disabled"
;
};
board_soc
:
soc
:
soc
@
ffe00000
{
ranges
=
<
0x0
0x0
0xffe00000
0x100000
>;
i2c
@
3100
{
wm8960
:
codec
@
1
a
{
compatible
=
"wlf,wm8960"
;
reg
=
<
0x1a
>;
/*
MCLK
source
is
a
stand
-
alone
oscillator
*/
clock
-
frequency
=
<
12288000
>;
};
rtc
@
68
{
compatible
=
"stm,m41t62"
;
reg
=
<
0x68
>;
};
adt7461
@
4
c
{
compatible
=
"adi,adt7461"
;
reg
=
<
0x4c
>;
};
zl6100
@
21
{
compatible
=
"isil,zl6100"
;
reg
=
<
0x21
>;
};
zl6100
@
24
{
compatible
=
"isil,zl6100"
;
reg
=
<
0x24
>;
};
zl6100
@
26
{
compatible
=
"isil,zl6100"
;
reg
=
<
0x26
>;
};
zl6100
@
29
{
compatible
=
"isil,zl6100"
;
reg
=
<
0x29
>;
};
};
spi
@
7000
{
flash
@
0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"spansion,m25p80"
;
reg
=
<
0
>;
spi
-
max
-
frequency
=
<
1000000
>;
partition
@
0
{
label
=
"full-spi-flash"
;
reg
=
<
0x00000000
0x00100000
>;
};
};
};
ssi
@
15000
{
fsl
,
mode
=
"i2s-slave"
;
codec
-
handle
=
<&
wm8960
>;
};
usb
@
22000
{
phy_type
=
"ulpi"
;
};
usb
@
23000
{
phy_type
=
"ulpi"
;
};
mdio
@
24000
{
phy0
:
ethernet
-
phy
@
0
{
interrupts
=
<
3
1
0
0
>;
reg
=
<
0x1
>;
};
phy1
:
ethernet
-
phy
@
1
{
interrupts
=
<
9
1
0
0
>;
reg
=
<
0x2
>;
};
};
mdio
@
25000
{
tbi0
:
tbi
-
phy
@
11
{
reg
=
<
0x11
>;
device_type
=
"tbi-phy"
;
};
};
ethernet
@
b0000
{
phy
-
handle
=
<&
phy0
>;
phy
-
connection
-
type
=
"rgmii-id"
;
};
ethernet
@
b1000
{
phy
-
handle
=
<&
phy1
>;
tbi
-
handle
=
<&
tbi0
>;
phy
-
connection
-
type
=
"sgmii"
;
};
};
pci0
:
pcie
@
ffe09000
{
ranges
=
<
0x2000000
0x0
0xe0000000
0
0xa0000000
0x0
0x20000000
0x1000000
0x0
0x00000000
0
0xffc10000
0x0
0x10000
>;
reg
=
<
0x0
0xffe09000
0
0x1000
>;
pcie
@
0
{
ranges
=
<
0x2000000
0x0
0xe0000000
0x2000000
0x0
0xe0000000
0x0
0x20000000
0x1000000
0x0
0x0
0x1000000
0x0
0x0
0x0
0x100000
>;
};
};
pci1
:
pcie
@
ffe0a000
{
ranges
=
<
0x2000000
0x0
0xe0000000
0
0xc0000000
0x0
0x20000000
0x1000000
0x0
0x00000000
0
0xffc20000
0x0
0x10000
>;
reg
=
<
0
0xffe0a000
0
0x1000
>;
pcie
@
0
{
ranges
=
<
0x2000000
0x0
0xe0000000
0x2000000
0x0
0xe0000000
0x0
0x20000000
0x1000000
0x0
0x0
0x1000000
0x0
0x0
0x0
0x100000
>;
};
};
pci2
:
pcie
@
ffe0b000
{
ranges
=
<
0x2000000
0x0
0xe0000000
0
0x80000000
0x0
0x20000000
0x1000000
0x0
0x00000000
0
0xffc00000
0x0
0x10000
>;
reg
=
<
0
0xffe0b000
0
0x1000
>;
pcie
@
0
{
ranges
=
<
0x2000000
0x0
0xe0000000
0x2000000
0x0
0xe0000000
0x0
0x20000000
0x1000000
0x0
0x0
0x1000000
0x0
0x0
0x0
0x100000
>;
};
};
};
/
include
/
"fsl/p1022si-post.dtsi"
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
已删除
100644 → 0
浏览文件 @
1e38b714
/*
*
P2020
RDB
Core0
Device
Tree
Source
in
CAMP
mode
.
*
*
In
CAMP
mode
,
each
core
needs
to
have
its
own
dts
.
Only
mpic
and
L2
cache
*
can
be
shared
,
all
the
other
devices
must
be
assigned
to
one
core
only
.
*
This
dts
file
allows
core0
to
have
memory
,
l2
,
i2c
,
spi
,
gpio
,
dma1
,
usb
,
*
eth1
,
eth2
,
sdhc
,
crypto
,
global
-
util
,
pci0
.
*
*
Copyright
2009
-
2011
Freescale
Semiconductor
Inc
.
*
*
This
program
is
free
software
;
you
can
redistribute
it
and
/
or
modify
it
*
under
the
terms
of
the
GNU
General
Public
License
as
published
by
the
*
Free
Software
Foundation
;
either
version
2
of
the
License
,
or
(
at
your
*
option
)
any
later
version
.
*/
/
include
/
"p2020rdb.dts"
/
{
model
=
"fsl,P2020RDB"
;
compatible
=
"fsl,P2020RDB"
,
"fsl,MPC85XXRDB-CAMP"
;
cpus
{
PowerPC
,
P2020
@
1
{
status
=
"disabled"
;
};
};
localbus
@
ffe05000
{
status
=
"disabled"
;
};
soc
@
ffe00000
{
serial1
:
serial
@
4600
{
status
=
"disabled"
;
};
dma
@
c300
{
status
=
"disabled"
;
};
enet0
:
ethernet
@
24000
{
status
=
"disabled"
;
};
mpic
:
pic
@
40000
{
protected
-
sources
=
<
42
76
77
78
79
/*
serial1
,
dma2
*/
29
30
34
26
/*
enet0
,
pci1
*/
0xe0
0xe1
0xe2
0xe3
/*
msi
*/
0xe4
0xe5
0xe6
0xe7
>;
};
msi
@
41600
{
status
=
"disabled"
;
};
};
pci0
:
pcie
@
ffe08000
{
status
=
"disabled"
;
};
pci2
:
pcie
@
ffe0a000
{
status
=
"disabled"
;
};
};
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
已删除
100644 → 0
浏览文件 @
1e38b714
/*
*
P2020
RDB
Core1
Device
Tree
Source
in
CAMP
mode
.
*
*
In
CAMP
mode
,
each
core
needs
to
have
its
own
dts
.
Only
mpic
and
L2
cache
*
can
be
shared
,
all
the
other
devices
must
be
assigned
to
one
core
only
.
*
This
dts
allows
core1
to
have
l2
,
dma2
,
eth0
,
pci1
,
msi
.
*
*
Please
note
to
add
"-b 1"
for
core1
's dts compiling.
*
* Copyright 2009-2011 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "p2020rdb.dts"
/ {
model = "fsl,P2020RDB";
compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
cpus {
PowerPC,P2020@0 {
status = "disabled";
};
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
ecm-law@0 {
status = "disabled";
};
ecm@1000 {
status = "disabled";
};
memory-controller@2000 {
status = "disabled";
};
i2c@3000 {
status = "disabled";
};
i2c@3100 {
status = "disabled";
};
serial0: serial@4500 {
status = "disabled";
};
spi@7000 {
status = "disabled";
};
gpio: gpio-controller@f000 {
status = "disabled";
};
dma@21300 {
status = "disabled";
};
usb@22000 {
status = "disabled";
};
mdio@24520 {
status = "disabled";
};
mdio@25520 {
status = "disabled";
};
mdio@26520 {
status = "disabled";
};
enet1: ethernet@25000 {
status = "disabled";
};
enet2: ethernet@26000 {
status = "disabled";
};
sdhci@2e000 {
status = "disabled";
};
crypto@30000 {
status = "disabled";
};
mpic: pic@40000 {
protected-sources = <
17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
16 20 21 22 23 28 /* L2, dma1, USB */
03 35 36 40 31 32 33 /* mdio, enet1, enet2 */
72 45 58 25 /* sdhci, crypto , pci */
>;
};
global-utilities@e0000 { //global utilities block
status = "disabled";
};
};
pci0: pcie@ffe08000 {
status = "disabled";
};
pci1: pcie@ffe09000 {
status = "disabled";
};
};
arch/powerpc/boot/dts/p2041rdb.dts
浏览文件 @
caa1d631
...
...
@@ -94,6 +94,10 @@
compatible
=
"pericom,pt7c4338"
;
reg
=
<
0x68
>;
};
adt7461
@
4
c
{
compatible
=
"adi,adt7461"
;
reg
=
<
0x4c
>;
};
};
i2c
@
118100
{
...
...
arch/powerpc/boot/dts/p3041ds.dts
浏览文件 @
caa1d631
...
...
@@ -98,6 +98,10 @@
reg
=
<
0x68
>;
interrupts
=
<
0x1
0x1
0
0
>;
};
adt7461
@
4
c
{
compatible
=
"adi,adt7461"
;
reg
=
<
0x4c
>;
};
};
};
...
...
arch/powerpc/boot/dts/p4080ds.dts
浏览文件 @
caa1d631
...
...
@@ -96,6 +96,10 @@
reg
=
<
0x68
>;
interrupts
=
<
0x1
0x1
0
0
>;
};
adt7461
@
4
c
{
compatible
=
"adi,adt7461"
;
reg
=
<
0x4c
>;
};
};
usb0
:
usb
@
210000
{
...
...
arch/powerpc/boot/dts/p5020ds.dts
浏览文件 @
caa1d631
...
...
@@ -98,6 +98,10 @@
reg
=
<
0x68
>;
interrupts
=
<
0x1
0x1
0
0
>;
};
adt7461
@
4
c
{
compatible
=
"adi,adt7461"
;
reg
=
<
0x4c
>;
};
};
};
...
...
arch/powerpc/boot/dts/p5040ds.dts
0 → 100644
浏览文件 @
caa1d631
/*
*
P5040DS
Device
Tree
Source
*
*
Copyright
2012
Freescale
Semiconductor
Inc
.
*
*
Redistribution
and
use
in
source
and
binary
forms
,
with
or
without
*
modification
,
are
permitted
provided
that
the
following
conditions
are
met
:
*
*
Redistributions
of
source
code
must
retain
the
above
copyright
*
notice
,
this
list
of
conditions
and
the
following
disclaimer
.
*
*
Redistributions
in
binary
form
must
reproduce
the
above
copyright
*
notice
,
this
list
of
conditions
and
the
following
disclaimer
in
the
*
documentation
and
/
or
other
materials
provided
with
the
distribution
.
*
*
Neither
the
name
of
Freescale
Semiconductor
nor
the
*
names
of
its
contributors
may
be
used
to
endorse
or
promote
products
*
derived
from
this
software
without
specific
prior
written
permission
.
*
*
*
ALTERNATIVELY
,
this
software
may
be
distributed
under
the
terms
of
the
*
GNU
General
Public
License
(
"GPL"
)
as
published
by
the
Free
Software
*
Foundation
,
either
version
2
of
that
License
or
(
at
your
option
)
any
*
later
version
.
*
*
This
software
is
provided
by
Freescale
Semiconductor
"as is"
and
any
*
express
or
implied
warranties
,
including
,
but
not
limited
to
,
the
implied
*
warranties
of
merchantability
and
fitness
for
a
particular
purpose
are
*
disclaimed
.
In
no
event
shall
Freescale
Semiconductor
be
liable
for
any
*
direct
,
indirect
,
incidental
,
special
,
exemplary
,
or
consequential
damages
*
(
including
,
but
not
limited
to
,
procurement
of
substitute
goods
or
services
;
*
loss
of
use
,
data
,
or
profits
;
or
business
interruption
)
however
caused
and
*
on
any
theory
of
liability
,
whether
in
contract
,
strict
liability
,
or
tort
*
(
including
negligence
or
otherwise
)
arising
in
any
way
out
of
the
use
of
this
*
software
,
even
if
advised
of
the
possibility
of
such
damage
.
*/
/
include
/
"fsl/p5040si-pre.dtsi"
/
{
model
=
"fsl,P5040DS"
;
compatible
=
"fsl,P5040DS"
;
#
address
-
cells
=
<
2
>;
#
size
-
cells
=
<
2
>;
interrupt
-
parent
=
<&
mpic
>;
memory
{
device_type
=
"memory"
;
};
dcsr
:
dcsr
@
f00000000
{
ranges
=
<
0x00000000
0xf
0x00000000
0x01008000
>;
};
soc
:
soc
@
ffe000000
{
ranges
=
<
0x00000000
0xf
0xfe000000
0x1000000
>;
reg
=
<
0xf
0xfe000000
0
0x00001000
>;
spi
@
110000
{
flash
@
0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"spansion,s25sl12801"
;
reg
=
<
0
>;
spi
-
max
-
frequency
=
<
40000000
>;
/*
input
clock
*/
partition
@
u
-
boot
{
label
=
"u-boot"
;
reg
=
<
0x00000000
0x00100000
>;
};
partition
@
kernel
{
label
=
"kernel"
;
reg
=
<
0x00100000
0x00500000
>;
};
partition
@
dtb
{
label
=
"dtb"
;
reg
=
<
0x00600000
0x00100000
>;
};
partition
@
fs
{
label
=
"file system"
;
reg
=
<
0x00700000
0x00900000
>;
};
};
};
i2c
@
118100
{
eeprom
@
51
{
compatible
=
"at24,24c256"
;
reg
=
<
0x51
>;
};
eeprom
@
52
{
compatible
=
"at24,24c256"
;
reg
=
<
0x52
>;
};
};
i2c
@
119100
{
rtc
@
68
{
compatible
=
"dallas,ds3232"
;
reg
=
<
0x68
>;
interrupts
=
<
0x1
0x1
0
0
>;
};
adt7461
@
4
c
{
compatible
=
"adi,adt7461"
;
reg
=
<
0x4c
>;
};
};
};
lbc
:
localbus
@
ffe124000
{
reg
=
<
0xf
0xfe124000
0
0x1000
>;
ranges
=
<
0
0
0xf
0xe8000000
0x08000000
2
0
0xf
0xffa00000
0x00040000
3
0
0xf
0xffdf0000
0x00008000
>;
flash
@
0
,
0
{
compatible
=
"cfi-flash"
;
reg
=
<
0
0
0x08000000
>;
bank
-
width
=
<
2
>;
device
-
width
=
<
2
>;
};
nand
@
2
,
0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"fsl,elbc-fcm-nand"
;
reg
=
<
0x2
0x0
0x40000
>;
partition
@
0
{
label
=
"NAND U-Boot Image"
;
reg
=
<
0x0
0x02000000
>;
};
partition
@
2000000
{
label
=
"NAND Root File System"
;
reg
=
<
0x02000000
0x10000000
>;
};
partition
@
12000000
{
label
=
"NAND Compressed RFS Image"
;
reg
=
<
0x12000000
0x08000000
>;
};
partition
@
1
a000000
{
label
=
"NAND Linux Kernel Image"
;
reg
=
<
0x1a000000
0x04000000
>;
};
partition
@
1e000000
{
label
=
"NAND DTB Image"
;
reg
=
<
0x1e000000
0x01000000
>;
};
partition
@
1f000000
{
label
=
"NAND Writable User area"
;
reg
=
<
0x1f000000
0x01000000
>;
};
};
board
-
control
@
3
,
0
{
compatible
=
"fsl,p5040ds-fpga"
,
"fsl,fpga-ngpixis"
;
reg
=
<
3
0
0x40
>;
};
};
pci0
:
pcie
@
ffe200000
{
reg
=
<
0xf
0xfe200000
0
0x1000
>;
ranges
=
<
0x02000000
0
0xe0000000
0xc
0x00000000
0x0
0x20000000
0x01000000
0
0x00000000
0xf
0xf8000000
0x0
0x00010000
>;
pcie
@
0
{
ranges
=
<
0x02000000
0
0xe0000000
0x02000000
0
0xe0000000
0
0x20000000
0x01000000
0
0x00000000
0x01000000
0
0x00000000
0
0x00010000
>;
};
};
pci1
:
pcie
@
ffe201000
{
reg
=
<
0xf
0xfe201000
0
0x1000
>;
ranges
=
<
0x02000000
0x0
0xe0000000
0xc
0x20000000
0x0
0x20000000
0x01000000
0x0
0x00000000
0xf
0xf8010000
0x0
0x00010000
>;
pcie
@
0
{
ranges
=
<
0x02000000
0
0xe0000000
0x02000000
0
0xe0000000
0
0x20000000
0x01000000
0
0x00000000
0x01000000
0
0x00000000
0
0x00010000
>;
};
};
pci2
:
pcie
@
ffe202000
{
reg
=
<
0xf
0xfe202000
0
0x1000
>;
ranges
=
<
0x02000000
0
0xe0000000
0xc
0x40000000
0
0x20000000
0x01000000
0
0x00000000
0xf
0xf8020000
0
0x00010000
>;
pcie
@
0
{
ranges
=
<
0x02000000
0
0xe0000000
0x02000000
0
0xe0000000
0
0x20000000
0x01000000
0
0x00000000
0x01000000
0
0x00000000
0
0x00010000
>;
};
};
};
/
include
/
"fsl/p5040si-post.dtsi"
arch/powerpc/configs/corenet32_smp_defconfig
浏览文件 @
caa1d631
...
...
@@ -27,6 +27,7 @@ CONFIG_P2041_RDB=y
CONFIG_P3041_DS=y
CONFIG_P4080_DS=y
CONFIG_P5020_DS=y
CONFIG_P5040_DS=y
CONFIG_HIGHMEM=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_MISC=m
...
...
arch/powerpc/configs/corenet64_smp_defconfig
浏览文件 @
caa1d631
...
...
@@ -23,6 +23,7 @@ CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
CONFIG_P5020_DS=y
CONFIG_P5040_DS=y
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
CONFIG_BINFMT_MISC=m
CONFIG_IRQ_ALL_CPUS=y
...
...
arch/powerpc/configs/mpc85xx_defconfig
浏览文件 @
caa1d631
...
...
@@ -30,6 +30,7 @@ CONFIG_MPC85xx_DS=y
CONFIG_MPC85xx_RDB=y
CONFIG_P1010_RDB=y
CONFIG_P1022_DS=y
CONFIG_P1022_RDK=y
CONFIG_P1023_RDS=y
CONFIG_SOCRATES=y
CONFIG_KSI8560=y
...
...
arch/powerpc/configs/mpc85xx_smp_defconfig
浏览文件 @
caa1d631
...
...
@@ -32,6 +32,7 @@ CONFIG_MPC85xx_DS=y
CONFIG_MPC85xx_RDB=y
CONFIG_P1010_RDB=y
CONFIG_P1022_DS=y
CONFIG_P1022_RDK=y
CONFIG_P1023_RDS=y
CONFIG_SOCRATES=y
CONFIG_KSI8560=y
...
...
arch/powerpc/include/asm/cacheflush.h
浏览文件 @
caa1d631
...
...
@@ -30,6 +30,8 @@ extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
extern
void
__flush_disable_L1
(
void
);
extern
void
__flush_icache_range
(
unsigned
long
,
unsigned
long
);
static
inline
void
flush_icache_range
(
unsigned
long
start
,
unsigned
long
stop
)
{
...
...
arch/powerpc/include/asm/fsl_guts.h
浏览文件 @
caa1d631
...
...
@@ -48,6 +48,8 @@ struct ccsr_guts {
__be32
dmuxcr
;
/* 0x.0068 - DMA Mux Control Register */
u8
res06c
[
0x70
-
0x6c
];
__be32
devdisr
;
/* 0x.0070 - Device Disable Control */
#define CCSR_GUTS_DEVDISR_TB1 0x00001000
#define CCSR_GUTS_DEVDISR_TB0 0x00004000
__be32
devdisr2
;
/* 0x.0074 - Device Disable Control 2 */
u8
res078
[
0x7c
-
0x78
];
__be32
pmjcr
;
/* 0x.007c - 4 Power Management Jog Control Register */
...
...
arch/powerpc/include/asm/fsl_ifc.h
浏览文件 @
caa1d631
...
...
@@ -768,22 +768,24 @@ struct fsl_ifc_gpcm {
*/
struct
fsl_ifc_regs
{
__be32
ifc_rev
;
u32
res1
[
0x
3
];
u32
res1
[
0x
2
];
struct
{
__be32
cspr_ext
;
__be32
cspr
;
u32
res2
[
0x2
]
;
u32
res2
;
}
cspr_cs
[
FSL_IFC_BANK_COUNT
];
u32
res3
[
0x1
8
];
u32
res3
[
0x1
9
];
struct
{
__be32
amask
;
u32
res4
[
0x2
];
}
amask_cs
[
FSL_IFC_BANK_COUNT
];
u32
res5
[
0x1
8
];
u32
res5
[
0x1
7
];
struct
{
__be32
csor_ext
;
__be32
csor
;
u32
res6
[
0x2
]
;
u32
res6
;
}
csor_cs
[
FSL_IFC_BANK_COUNT
];
u32
res7
[
0x1
8
];
u32
res7
[
0x1
9
];
struct
{
__be32
ftim
[
4
];
u32
res8
[
0x8
];
...
...
arch/powerpc/include/asm/mpic.h
浏览文件 @
caa1d631
...
...
@@ -63,6 +63,7 @@
*/
#define MPIC_TIMER_BASE 0x01100
#define MPIC_TIMER_STRIDE 0x40
#define MPIC_TIMER_GROUP_STRIDE 0x1000
#define MPIC_TIMER_CURRENT_CNT 0x00000
#define MPIC_TIMER_BASE_CNT 0x00010
...
...
@@ -110,10 +111,16 @@
#define MPIC_VECPRI_SENSE_MASK 0x00400000
#define MPIC_IRQ_DESTINATION 0x00010
#define MPIC_FSL_BRR1 0x00000
#define MPIC_FSL_BRR1_VER 0x0000ffff
#define MPIC_MAX_IRQ_SOURCES 2048
#define MPIC_MAX_CPUS 32
#define MPIC_MAX_ISU 32
#define MPIC_MAX_ERR 32
#define MPIC_FSL_ERR_INT 16
/*
* Tsi108 implementation of MPIC has many differences from the original one
*/
...
...
@@ -266,6 +273,7 @@ struct mpic
struct
irq_chip
hc_ipi
;
#endif
struct
irq_chip
hc_tm
;
struct
irq_chip
hc_err
;
const
char
*
name
;
/* Flags */
unsigned
int
flags
;
...
...
@@ -279,6 +287,8 @@ struct mpic
/* vector numbers used for internal sources (ipi/timers) */
unsigned
int
ipi_vecs
[
4
];
unsigned
int
timer_vecs
[
8
];
/* vector numbers used for FSL MPIC error interrupts */
unsigned
int
err_int_vecs
[
MPIC_MAX_ERR
];
/* Spurious vector to program into unused sources */
unsigned
int
spurious_vec
;
...
...
@@ -296,11 +306,15 @@ struct mpic
phys_addr_t
paddr
;
/* The various ioremap'ed bases */
struct
mpic_reg_bank
thiscpuregs
;
struct
mpic_reg_bank
gregs
;
struct
mpic_reg_bank
tmregs
;
struct
mpic_reg_bank
cpuregs
[
MPIC_MAX_CPUS
];
struct
mpic_reg_bank
isus
[
MPIC_MAX_ISU
];
/* ioremap'ed base for error interrupt registers */
u32
__iomem
*
err_regs
;
/* Protected sources */
unsigned
long
*
protected
;
...
...
@@ -365,6 +379,11 @@ struct mpic
#define MPIC_NO_RESET 0x00004000
/* Freescale MPIC (compatible includes "fsl,mpic") */
#define MPIC_FSL 0x00008000
/* Freescale MPIC supports EIMR (error interrupt mask register).
* This flag is set for MPIC version >= 4.1 (version determined
* from the BRR1 register).
*/
#define MPIC_FSL_HAS_EIMR 0x00010000
/* MPIC HW modification ID */
#define MPIC_REGSET_MASK 0xf0000000
...
...
arch/powerpc/include/asm/smp.h
浏览文件 @
caa1d631
...
...
@@ -65,6 +65,7 @@ int generic_cpu_disable(void);
void
generic_cpu_die
(
unsigned
int
cpu
);
void
generic_mach_cpu_die
(
void
);
void
generic_set_cpu_dead
(
unsigned
int
cpu
);
void
generic_set_cpu_up
(
unsigned
int
cpu
);
int
generic_check_cpu_restart
(
unsigned
int
cpu
);
#endif
...
...
@@ -190,6 +191,7 @@ extern unsigned long __secondary_hold_spinloop;
extern
unsigned
long
__secondary_hold_acknowledge
;
extern
char
__secondary_hold
;
extern
void
__early_start
(
void
);
#endif
/* __ASSEMBLY__ */
#endif
/* __KERNEL__ */
...
...
arch/powerpc/include/asm/swiotlb.h
浏览文件 @
caa1d631
...
...
@@ -22,4 +22,10 @@ int __init swiotlb_setup_bus_notifier(void);
extern
void
pci_dma_dev_setup_swiotlb
(
struct
pci_dev
*
pdev
);
#ifdef CONFIG_SWIOTLB
void
swiotlb_detect_4g
(
void
);
#else
static
inline
void
swiotlb_detect_4g
(
void
)
{}
#endif
#endif
/* __ASM_SWIOTLB_H */
arch/powerpc/kernel/cpu_setup_fsl_booke.S
浏览文件 @
caa1d631
...
...
@@ -16,6 +16,8 @@
#include <asm/processor.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/mmu-book3e.h>
#include <asm/asm-offsets.h>
_GLOBAL
(
__e500_icache_setup
)
mfspr
r0
,
SPRN_L1CSR1
...
...
@@ -73,27 +75,81 @@ _GLOBAL(__setup_cpu_e500v2)
mtlr
r4
blr
_GLOBAL
(
__setup_cpu_e500mc
)
mr
r5
,
r4
mflr
r
4
_GLOBAL
(
__setup_cpu_e5500
)
mflr
r
5
bl
__e500_icache_setup
bl
__e500_dcache_setup
bl
__setup_e500mc_ivors
mtlr
r4
/
*
*
We
only
want
to
touch
IVOR38
-
41
if
we
're running on hardware
*
that
supports
category
E
.
HV
.
The
architectural
way
to
determine
*
this
is
MMUCFG
[
LPIDSIZE
]
.
*/
mfspr
r3
,
SPRN_MMUCFG
rlwinm
.
r3
,
r3
,
0
,
MMUCFG_LPIDSIZE
beq
1
f
bl
__setup_ehv_ivors
b
2
f
1
:
lwz
r3
,
CPU_SPEC_FEATURES
(
r4
)
/
*
We
need
this
check
as
cpu_setup
is
also
called
for
*
the
secondary
cores
.
So
,
if
we
have
already
cleared
*
the
feature
on
the
primary
core
,
avoid
doing
it
on
the
*
secondary
core
.
*/
andis
.
r6
,
r3
,
CPU_FTR_EMB_HV
@
h
beq
2
f
rlwinm
r3
,
r3
,
0
,
~
CPU_FTR_EMB_HV
stw
r3
,
CPU_SPEC_FEATURES
(
r4
)
2
:
mtlr
r5
blr
#endif
/*
Right
now
,
restore
and
setup
are
the
same
thing
*/
#ifdef CONFIG_PPC_BOOK3E_64
_GLOBAL
(
__restore_cpu_e5500
)
_GLOBAL
(
__setup_cpu_e5500
)
mflr
r4
bl
__e500_icache_setup
bl
__e500_dcache_setup
#ifdef CONFIG_PPC_BOOK3E_64
bl
.
__setup_base_ivors
bl
.
setup_perfmon_ivor
bl
.
setup_doorbell_ivors
/
*
*
We
only
want
to
touch
IVOR38
-
41
if
we
're running on hardware
*
that
supports
category
E
.
HV
.
The
architectural
way
to
determine
*
this
is
MMUCFG
[
LPIDSIZE
]
.
*/
mfspr
r10
,
SPRN_MMUCFG
rlwinm
.
r10
,
r10
,
0
,
MMUCFG_LPIDSIZE
beq
1
f
bl
.
setup_ehv_ivors
#else
bl
__setup_e500mc_ivors
#endif
1
:
mtlr
r4
blr
_GLOBAL
(
__setup_cpu_e5500
)
mflr
r5
bl
__e500_icache_setup
bl
__e500_dcache_setup
bl
.
__setup_base_ivors
bl
.
setup_perfmon_ivor
bl
.
setup_doorbell_ivors
/
*
*
We
only
want
to
touch
IVOR38
-
41
if
we
're running on hardware
*
that
supports
category
E
.
HV
.
The
architectural
way
to
determine
*
this
is
MMUCFG
[
LPIDSIZE
]
.
*/
mfspr
r10
,
SPRN_MMUCFG
rlwinm
.
r10
,
r10
,
0
,
MMUCFG_LPIDSIZE
beq
1
f
bl
.
setup_ehv_ivors
b
2
f
1
:
ld
r10
,
CPU_SPEC_FEATURES
(
r4
)
LOAD_REG_IMMEDIATE
(
r9
,
CPU_FTR_EMB_HV
)
andc
r10
,
r10
,
r9
std
r10
,
CPU_SPEC_FEATURES
(
r4
)
2
:
mtlr
r5
blr
#endif
arch/powerpc/kernel/cputable.c
浏览文件 @
caa1d631
...
...
@@ -2016,7 +2016,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
.
oprofile_cpu_type
=
"ppc/e500mc"
,
.
oprofile_type
=
PPC_OPROFILE_FSL_EMB
,
.
cpu_setup
=
__setup_cpu_e5500
,
#ifndef CONFIG_PPC32
.
cpu_restore
=
__restore_cpu_e5500
,
#endif
.
machine_check
=
machine_check_e500mc
,
.
platform
=
"ppce5500"
,
},
...
...
@@ -2034,7 +2036,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
.
oprofile_cpu_type
=
"ppc/e6500"
,
.
oprofile_type
=
PPC_OPROFILE_FSL_EMB
,
.
cpu_setup
=
__setup_cpu_e5500
,
#ifndef CONFIG_PPC32
.
cpu_restore
=
__restore_cpu_e5500
,
#endif
.
machine_check
=
machine_check_e500mc
,
.
platform
=
"ppce6500"
,
},
...
...
arch/powerpc/kernel/dma-swiotlb.c
浏览文件 @
caa1d631
...
...
@@ -105,3 +105,23 @@ int __init swiotlb_setup_bus_notifier(void)
&
ppc_swiotlb_plat_bus_notifier
);
return
0
;
}
void
swiotlb_detect_4g
(
void
)
{
if
((
memblock_end_of_DRAM
()
-
1
)
>
0xffffffff
)
ppc_swiotlb_enable
=
1
;
}
static
int
__init
swiotlb_late_init
(
void
)
{
if
(
ppc_swiotlb_enable
)
{
swiotlb_print_info
();
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
}
else
{
swiotlb_free
();
}
return
0
;
}
subsys_initcall
(
swiotlb_late_init
);
arch/powerpc/kernel/exceptions-64e.S
浏览文件 @
caa1d631
...
...
@@ -1356,25 +1356,11 @@ _GLOBAL(setup_perfmon_ivor)
_GLOBAL
(
setup_doorbell_ivors
)
SET_IVOR
(36,
0x280
)
/*
Processor
Doorbell
*/
SET_IVOR
(37,
0x2a0
)
/*
Processor
Doorbell
Crit
*/
/
*
Check
MMUCFG
[
LPIDSIZE
]
to
determine
if
we
have
category
E
.
HV
*/
mfspr
r10
,
SPRN_MMUCFG
rlwinm
.
r10
,
r10
,
0
,
MMUCFG_LPIDSIZE
beqlr
SET_IVOR
(38,
0x2c0
)
/*
Guest
Processor
Doorbell
*/
SET_IVOR
(39,
0x2e0
)
/*
Guest
Processor
Doorbell
Crit
/
MC
*/
blr
_GLOBAL
(
setup_ehv_ivors
)
/
*
*
We
may
be
running
as
a
guest
and
lack
E
.
HV
even
on
a
chip
*
that
normally
has
it
.
*/
mfspr
r10
,
SPRN_MMUCFG
rlwinm
.
r10
,
r10
,
0
,
MMUCFG_LPIDSIZE
beqlr
SET_IVOR
(40,
0x300
)
/*
Embedded
Hypervisor
System
Call
*/
SET_IVOR
(41,
0x320
)
/*
Embedded
Hypervisor
Privilege
*/
SET_IVOR
(38,
0x2c0
)
/*
Guest
Processor
Doorbell
*/
SET_IVOR
(39,
0x2e0
)
/*
Guest
Processor
Doorbell
Crit
/
MC
*/
blr
arch/powerpc/kernel/head_fsl_booke.S
浏览文件 @
caa1d631
...
...
@@ -895,15 +895,11 @@ _GLOBAL(__setup_e500mc_ivors)
mtspr
SPRN_IVOR36
,
r3
li
r3
,
CriticalDoorbell
@
l
mtspr
SPRN_IVOR37
,
r3
sync
blr
/
*
*
We
only
want
to
touch
IVOR38
-
41
if
we
're running on hardware
*
that
supports
category
E
.
HV
.
The
architectural
way
to
determine
*
this
is
MMUCFG
[
LPIDSIZE
]
.
*/
mfspr
r3
,
SPRN_MMUCFG
andis
.
r3
,
r3
,
MMUCFG_LPIDSIZE
@
h
beq
no_hv
/*
setup
ehv
ivors
for
*/
_GLOBAL
(
__setup_ehv_ivors
)
li
r3
,
GuestDoorbell
@
l
mtspr
SPRN_IVOR38
,
r3
li
r3
,
CriticalGuestDoorbell
@
l
...
...
@@ -912,14 +908,8 @@ _GLOBAL(__setup_e500mc_ivors)
mtspr
SPRN_IVOR40
,
r3
li
r3
,
Ehvpriv
@
l
mtspr
SPRN_IVOR41
,
r3
skip_hv_ivors
:
sync
blr
no_hv
:
lwz
r3
,
CPU_SPEC_FEATURES
(
r5
)
rlwinm
r3
,
r3
,
0
,
~
CPU_FTR_EMB_HV
stw
r3
,
CPU_SPEC_FEATURES
(
r5
)
b
skip_hv_ivors
#ifdef CONFIG_SPE
/*
...
...
@@ -1043,6 +1033,34 @@ _GLOBAL(flush_dcache_L1)
blr
/*
Flush
L1
d
-
cache
,
invalidate
and
disable
d
-
cache
and
i
-
cache
*/
_GLOBAL
(
__flush_disable_L1
)
mflr
r10
bl
flush_dcache_L1
/*
Flush
L1
d
-
cache
*/
mtlr
r10
mfspr
r4
,
SPRN_L1CSR0
/*
Invalidate
and
disable
d
-
cache
*/
li
r5
,
2
rlwimi
r4
,
r5
,
0
,
3
msync
isync
mtspr
SPRN_L1CSR0
,
r4
isync
1
:
mfspr
r4
,
SPRN_L1CSR0
/*
Wait
for
the
invalidate
to
finish
*/
andi
.
r4
,
r4
,
2
bne
1
b
mfspr
r4
,
SPRN_L1CSR1
/*
Invalidate
and
disable
i
-
cache
*/
li
r5
,
2
rlwimi
r4
,
r5
,
0
,
3
mtspr
SPRN_L1CSR1
,
r4
isync
blr
#ifdef CONFIG_SMP
/*
When
we
get
here
,
r24
needs
to
hold
the
CPU
#
*/
.
globl
__secondary_start
...
...
arch/powerpc/kernel/smp.c
浏览文件 @
caa1d631
...
...
@@ -102,7 +102,7 @@ int __devinit smp_generic_kick_cpu(int nr)
* Ok it's not there, so it might be soft-unplugged, let's
* try to bring it back
*/
per_cpu
(
cpu_state
,
nr
)
=
CPU_UP_PREPARE
;
generic_set_cpu_up
(
nr
)
;
smp_wmb
();
smp_send_reschedule
(
nr
);
#endif
/* CONFIG_HOTPLUG_CPU */
...
...
@@ -413,6 +413,16 @@ void generic_set_cpu_dead(unsigned int cpu)
per_cpu
(
cpu_state
,
cpu
)
=
CPU_DEAD
;
}
/*
* The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
* the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
* which makes the delay in generic_cpu_die() not happen.
*/
void
generic_set_cpu_up
(
unsigned
int
cpu
)
{
per_cpu
(
cpu_state
,
cpu
)
=
CPU_UP_PREPARE
;
}
int
generic_check_cpu_restart
(
unsigned
int
cpu
)
{
return
per_cpu
(
cpu_state
,
cpu
)
==
CPU_UP_PREPARE
;
...
...
arch/powerpc/mm/mem.c
浏览文件 @
caa1d631
...
...
@@ -300,8 +300,7 @@ void __init mem_init(void)
unsigned
long
reservedpages
=
0
,
codesize
,
initsize
,
datasize
,
bsssize
;
#ifdef CONFIG_SWIOTLB
if
(
ppc_swiotlb_enable
)
swiotlb_init
(
1
);
swiotlb_init
(
0
);
#endif
num_physpages
=
memblock_phys_mem_size
()
>>
PAGE_SHIFT
;
...
...
arch/powerpc/platforms/44x/currituck.c
浏览文件 @
caa1d631
...
...
@@ -21,7 +21,6 @@
*/
#include <linux/init.h>
#include <linux/memblock.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/rtc.h>
...
...
@@ -159,13 +158,8 @@ static void __init ppc47x_setup_arch(void)
/* No need to check the DMA config as we /know/ our windows are all of
* RAM. Lets hope that doesn't change */
#ifdef CONFIG_SWIOTLB
if
((
memblock_end_of_DRAM
()
-
1
)
>
0xffffffff
)
{
ppc_swiotlb_enable
=
1
;
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
}
#endif
swiotlb_detect_4g
();
ppc47x_smp_init
();
}
...
...
arch/powerpc/platforms/85xx/Kconfig
浏览文件 @
caa1d631
...
...
@@ -104,6 +104,13 @@ config P1022_DS
help
This option enables support for the Freescale P1022DS reference board.
config P1022_RDK
bool "Freescale / iVeia P1022 RDK"
select DEFAULT_UIMAGE
help
This option enables support for the Freescale / iVeia P1022RDK
reference board.
config P1023_RDS
bool "Freescale P1023 RDS"
select DEFAULT_UIMAGE
...
...
@@ -254,6 +261,20 @@ config P5020_DS
help
This option enables support for the P5020 DS board
config P5040_DS
bool "Freescale P5040 DS"
select DEFAULT_UIMAGE
select E500
select PPC_E500MC
select PHYS_64BIT
select SWIOTLB
select ARCH_REQUIRE_GPIOLIB
select GPIO_MPC8XXX
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
help
This option enables support for the P5040 DS board
config PPC_QEMU_E500
bool "QEMU generic e500 platform"
depends on EXPERIMENTAL
...
...
arch/powerpc/platforms/85xx/Makefile
浏览文件 @
caa1d631
...
...
@@ -15,11 +15,13 @@ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
obj-$(CONFIG_MPC85xx_RDB)
+=
mpc85xx_rdb.o
obj-$(CONFIG_P1010_RDB)
+=
p1010rdb.o
obj-$(CONFIG_P1022_DS)
+=
p1022_ds.o
obj-$(CONFIG_P1022_RDK)
+=
p1022_rdk.o
obj-$(CONFIG_P1023_RDS)
+=
p1023_rds.o
obj-$(CONFIG_P2041_RDB)
+=
p2041_rdb.o corenet_ds.o
obj-$(CONFIG_P3041_DS)
+=
p3041_ds.o corenet_ds.o
obj-$(CONFIG_P4080_DS)
+=
p4080_ds.o corenet_ds.o
obj-$(CONFIG_P5020_DS)
+=
p5020_ds.o corenet_ds.o
obj-$(CONFIG_P5040_DS)
+=
p5040_ds.o corenet_ds.o
obj-$(CONFIG_STX_GP3)
+=
stx_gp3.o
obj-$(CONFIG_TQM85xx)
+=
tqm85xx.o
obj-$(CONFIG_SBC8548)
+=
sbc8548.o
...
...
arch/powerpc/platforms/85xx/common.c
浏览文件 @
caa1d631
...
...
@@ -27,6 +27,16 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
{
.
compatible
=
"fsl,mpc8548-guts"
,
},
/* Probably unnecessary? */
{
.
compatible
=
"gpio-leds"
,
},
/* For all PCI controllers */
{
.
compatible
=
"fsl,mpc8540-pci"
,
},
{
.
compatible
=
"fsl,mpc8548-pcie"
,
},
{
.
compatible
=
"fsl,p1022-pcie"
,
},
{
.
compatible
=
"fsl,p1010-pcie"
,
},
{
.
compatible
=
"fsl,p1023-pcie"
,
},
{
.
compatible
=
"fsl,p4080-pcie"
,
},
{
.
compatible
=
"fsl,qoriq-pcie-v2.4"
,
},
{
.
compatible
=
"fsl,qoriq-pcie-v2.3"
,
},
{
.
compatible
=
"fsl,qoriq-pcie-v2.2"
,
},
{},
};
...
...
arch/powerpc/platforms/85xx/corenet_ds.c
浏览文件 @
caa1d631
...
...
@@ -16,7 +16,6 @@
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>
#include <asm/time.h>
#include <asm/machdep.h>
...
...
@@ -52,37 +51,16 @@ void __init corenet_ds_pic_init(void)
*/
void
__init
corenet_ds_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
struct
pci_controller
*
hose
;
#endif
dma_addr_t
max
=
0xffffffff
;
mpc85xx_smp_init
();
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,p4080-pcie"
)
||
of_device_is_compatible
(
np
,
"fsl,qoriq-pcie-v2.2"
))
{
fsl_add_bridge
(
np
,
0
);
hose
=
pci_find_hose_for_OF_device
(
np
);
max
=
min
(
max
,
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
);
}
}
#ifdef CONFIG_PPC64
#if defined(CONFIG_PCI) && defined(CONFIG_PPC64)
pci_devs_phb_init
();
#endif
#endif
#ifdef CONFIG_SWIOTLB
if
((
memblock_end_of_DRAM
()
-
1
)
>
max
)
{
ppc_swiotlb_enable
=
1
;
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
}
#endif
fsl_pci_assign_primary
();
swiotlb_detect_4g
();
pr_info
(
"%s board from Freescale Semiconductor
\n
"
,
ppc_md
.
name
);
}
...
...
@@ -99,6 +77,12 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
{
.
compatible
=
"fsl,qoriq-pcie-v2.2"
,
},
{
.
compatible
=
"fsl,qoriq-pcie-v2.3"
,
},
{
.
compatible
=
"fsl,qoriq-pcie-v2.4"
,
},
/* The following two are for the Freescale hypervisor */
{
.
name
=
"hypervisor"
,
...
...
arch/powerpc/platforms/85xx/ge_imp3a.c
浏览文件 @
caa1d631
...
...
@@ -22,7 +22,6 @@
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
#include <asm/time.h>
#include <asm/machdep.h>
...
...
@@ -84,53 +83,39 @@ void __init ge_imp3a_pic_init(void)
of_node_put
(
cascade_node
);
}
#ifdef CONFIG_PCI
static
int
primary_phb_addr
;
#endif
/* CONFIG_PCI */
/*
* Setup the architecture
*/
static
void
__init
ge_imp3a_setup_arch
(
void
)
static
void
ge_imp3a_pci_assign_primary
(
void
)
{
struct
device_node
*
regs
;
#ifdef CONFIG_PCI
struct
device_node
*
np
;
struct
pci_controller
*
hose
;
#endif
dma_addr_t
max
=
0xffffffff
;
struct
resource
rsrc
;
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"ge_imp3a_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8540-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
)
||
of_device_is_compatible
(
np
,
"fsl,p2020-pcie"
))
{
struct
resource
rsrc
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
primary_phb_addr
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
hose
=
pci_find_hose_for_OF_device
(
np
);
max
=
min
(
max
,
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
);
if
((
rsrc
.
start
&
0xfffff
)
==
0x9000
)
fsl_pci_primary
=
np
;
}
}
#endif
}
/*
* Setup the architecture
*/
static
void
__init
ge_imp3a_setup_arch
(
void
)
{
struct
device_node
*
regs
;
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"ge_imp3a_setup_arch()"
,
0
);
mpc85xx_smp_init
();
#ifdef CONFIG_SWIOTLB
if
((
memblock_end_of_DRAM
()
-
1
)
>
max
)
{
ppc_swiotlb_enable
=
1
;
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
}
#endif
ge_imp3a_pci_assign_primary
();
swiotlb_detect_4g
();
/* Remap basic board registers */
regs
=
of_find_compatible_node
(
NULL
,
NULL
,
"ge,imp3a-fpga-regs"
);
...
...
@@ -215,17 +200,10 @@ static int __init ge_imp3a_probe(void)
{
unsigned
long
root
=
of_get_flat_dt_root
();
if
(
of_flat_dt_is_compatible
(
root
,
"ge,IMP3A"
))
{
#ifdef CONFIG_PCI
primary_phb_addr
=
0x9000
;
#endif
return
1
;
}
return
0
;
return
of_flat_dt_is_compatible
(
root
,
"ge,IMP3A"
);
}
machine_
device
_initcall
(
ge_imp3a
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
ge_imp3a
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
ge_imp3a
,
swiotlb_setup_bus_notifier
);
...
...
arch/powerpc/platforms/85xx/mpc8536_ds.c
浏览文件 @
caa1d631
...
...
@@ -17,7 +17,6 @@
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
#include <asm/time.h>
#include <asm/machdep.h>
...
...
@@ -46,46 +45,17 @@ void __init mpc8536_ds_pic_init(void)
*/
static
void
__init
mpc8536_ds_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
struct
pci_controller
*
hose
;
#endif
dma_addr_t
max
=
0xffffffff
;
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"mpc8536_ds_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8540-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
))
{
struct
resource
rsrc
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
0x8000
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
hose
=
pci_find_hose_for_OF_device
(
np
);
max
=
min
(
max
,
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
);
}
}
#endif
fsl_pci_assign_primary
();
#ifdef CONFIG_SWIOTLB
if
((
memblock_end_of_DRAM
()
-
1
)
>
max
)
{
ppc_swiotlb_enable
=
1
;
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
}
#endif
swiotlb_detect_4g
();
printk
(
"MPC8536 DS board from Freescale Semiconductor
\n
"
);
}
machine_
device
_initcall
(
mpc8536_ds
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
mpc8536_ds
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
mpc8536_ds
,
swiotlb_setup_bus_notifier
);
...
...
arch/powerpc/platforms/85xx/mpc85xx_ads.c
浏览文件 @
caa1d631
...
...
@@ -137,10 +137,6 @@ static void __init init_ioports(void)
static
void
__init
mpc85xx_ads_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"mpc85xx_ads_setup_arch()"
,
0
);
...
...
@@ -150,11 +146,10 @@ static void __init mpc85xx_ads_setup_arch(void)
#endif
#ifdef CONFIG_PCI
for_each_compatible_node
(
np
,
"pci"
,
"fsl,mpc8540-pci"
)
fsl_add_bridge
(
np
,
1
);
ppc_md
.
pci_exclude_device
=
mpc85xx_exclude_device
;
#endif
fsl_pci_assign_primary
();
}
static
void
mpc85xx_ads_show_cpuinfo
(
struct
seq_file
*
m
)
...
...
@@ -173,7 +168,7 @@ static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
seq_printf
(
m
,
"PLL setting
\t
: 0x%x
\n
"
,
((
phid1
>>
24
)
&
0x3f
));
}
machine_
device
_initcall
(
mpc85xx_ads
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
mpc85xx_ads
,
mpc85xx_common_publish_devices
);
/*
* Called very early, device-tree isn't unflattened
...
...
arch/powerpc/platforms/85xx/mpc85xx_cds.c
浏览文件 @
caa1d631
...
...
@@ -276,6 +276,33 @@ machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
#endif
/* CONFIG_PPC_I8259 */
static
void
mpc85xx_cds_pci_assign_primary
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
if
(
fsl_pci_primary
)
return
;
/*
* MPC85xx_CDS has ISA bridge but unfortunately there is no
* isa node in device tree. We now looking for i8259 node as
* a workaround for such a broken device tree. This routine
* is for complying to all device trees.
*/
np
=
of_find_node_by_name
(
NULL
,
"i8259"
);
while
((
fsl_pci_primary
=
of_get_parent
(
np
)))
{
of_node_put
(
np
);
np
=
fsl_pci_primary
;
if
((
of_device_is_compatible
(
np
,
"fsl,mpc8540-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
))
&&
of_device_is_available
(
np
))
return
;
}
#endif
}
/*
* Setup the architecture
*/
...
...
@@ -309,21 +336,12 @@ static void __init mpc85xx_cds_setup_arch(void)
}
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8540-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
))
{
struct
resource
rsrc
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
0x8000
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
}
}
ppc_md
.
pci_irq_fixup
=
mpc85xx_cds_pci_irq_fixup
;
ppc_md
.
pci_exclude_device
=
mpc85xx_exclude_device
;
#endif
mpc85xx_cds_pci_assign_primary
();
fsl_pci_assign_primary
();
}
static
void
mpc85xx_cds_show_cpuinfo
(
struct
seq_file
*
m
)
...
...
@@ -355,7 +373,7 @@ static int __init mpc85xx_cds_probe(void)
return
of_flat_dt_is_compatible
(
root
,
"MPC85xxCDS"
);
}
machine_
device
_initcall
(
mpc85xx_cds
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
mpc85xx_cds
,
mpc85xx_common_publish_devices
);
define_machine
(
mpc85xx_cds
)
{
.
name
=
"MPC85xx CDS"
,
...
...
arch/powerpc/platforms/85xx/mpc85xx_ds.c
浏览文件 @
caa1d631
...
...
@@ -20,7 +20,6 @@
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
#include <asm/time.h>
#include <asm/machdep.h>
...
...
@@ -129,13 +128,11 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
}
#endif
/* CONFIG_PCI */
static
void
__init
mpc85xx_ds_
pc
i_init
(
void
)
static
void
__init
mpc85xx_ds_
ul
i_init
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
node
;
fsl_pci_init
();
/* See if we have a ULI under the primary */
node
=
of_find_node_by_name
(
NULL
,
"uli1575"
);
...
...
@@ -159,7 +156,9 @@ static void __init mpc85xx_ds_setup_arch(void)
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"mpc85xx_ds_setup_arch()"
,
0
);
mpc85xx_ds_pci_init
();
swiotlb_detect_4g
();
fsl_pci_assign_primary
();
mpc85xx_ds_uli_init
();
mpc85xx_smp_init
();
printk
(
"MPC85xx DS board from Freescale Semiconductor
\n
"
);
...
...
@@ -175,9 +174,9 @@ static int __init mpc8544_ds_probe(void)
return
!!
of_flat_dt_is_compatible
(
root
,
"MPC8544DS"
);
}
machine_
device
_initcall
(
mpc8544_ds
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
mpc8572_ds
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p2020_ds
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
mpc8544_ds
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
mpc8572_ds
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p2020_ds
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
mpc8544_ds
,
swiotlb_setup_bus_notifier
);
machine_arch_initcall
(
mpc8572_ds
,
swiotlb_setup_bus_notifier
);
...
...
arch/powerpc/platforms/85xx/mpc85xx_mds.c
浏览文件 @
caa1d631
...
...
@@ -327,44 +327,16 @@ static void __init mpc85xx_mds_qeic_init(void) { }
static
void
__init
mpc85xx_mds_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
pci_controller
*
hose
;
struct
device_node
*
np
;
#endif
dma_addr_t
max
=
0xffffffff
;
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"mpc85xx_mds_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8540-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
))
{
struct
resource
rsrc
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
0x8000
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
hose
=
pci_find_hose_for_OF_device
(
np
);
max
=
min
(
max
,
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
);
}
}
#endif
mpc85xx_smp_init
();
mpc85xx_mds_qe_init
();
#ifdef CONFIG_SWIOTLB
if
((
memblock_end_of_DRAM
()
-
1
)
>
max
)
{
ppc_swiotlb_enable
=
1
;
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
}
#endif
fsl_pci_assign_primary
();
swiotlb_detect_4g
();
}
...
...
@@ -409,9 +381,9 @@ static int __init mpc85xx_publish_devices(void)
return
mpc85xx_common_publish_devices
();
}
machine_
device
_initcall
(
mpc8568_mds
,
mpc85xx_publish_devices
);
machine_
device
_initcall
(
mpc8569_mds
,
mpc85xx_publish_devices
);
machine_
device
_initcall
(
p1021_mds
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
mpc8568_mds
,
mpc85xx_publish_devices
);
machine_
arch
_initcall
(
mpc8569_mds
,
mpc85xx_publish_devices
);
machine_
arch
_initcall
(
p1021_mds
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
mpc8568_mds
,
swiotlb_setup_bus_notifier
);
machine_arch_initcall
(
mpc8569_mds
,
swiotlb_setup_bus_notifier
);
...
...
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
浏览文件 @
caa1d631
...
...
@@ -86,23 +86,17 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static
void
__init
mpc85xx_rdb_setup_arch
(
void
)
{
#if
defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
#if
def CONFIG_QUICC_ENGINE
struct
device_node
*
np
;
#endif
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"mpc85xx_rdb_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
))
fsl_add_bridge
(
np
,
0
);
}
#endif
mpc85xx_smp_init
();
fsl_pci_assign_primary
();
#ifdef CONFIG_QUICC_ENGINE
np
=
of_find_compatible_node
(
NULL
,
NULL
,
"fsl,qe"
);
if
(
!
np
)
{
...
...
@@ -161,15 +155,15 @@ static void __init mpc85xx_rdb_setup_arch(void)
printk
(
KERN_INFO
"MPC85xx RDB board from Freescale Semiconductor
\n
"
);
}
machine_
device
_initcall
(
p2020_rdb
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p2020_rdb_pc
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p1020_mbg_pc
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p1020_rdb
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p1020_rdb_pc
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p1020_utm_pc
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p1021_rdb_pc
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p1025_rdb
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
p1024_rdb
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p2020_rdb
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p2020_rdb_pc
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1020_mbg_pc
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1020_rdb
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1020_rdb_pc
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1020_utm_pc
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1021_rdb_pc
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1025_rdb
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1024_rdb
,
mpc85xx_common_publish_devices
);
/*
* Called very early, device-tree isn't unflattened
...
...
arch/powerpc/platforms/85xx/p1010rdb.c
浏览文件 @
caa1d631
...
...
@@ -46,25 +46,15 @@ void __init p1010_rdb_pic_init(void)
*/
static
void
__init
p1010_rdb_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"p1010_rdb_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,p1010-pcie"
))
fsl_add_bridge
(
np
,
0
);
}
#endif
fsl_pci_assign_primary
();
printk
(
KERN_INFO
"P1010 RDB board from Freescale Semiconductor
\n
"
);
}
machine_
device
_initcall
(
p1010_rdb
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1010_rdb
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1010_rdb
,
swiotlb_setup_bus_notifier
);
/*
...
...
arch/powerpc/platforms/85xx/p1022_ds.c
浏览文件 @
caa1d631
...
...
@@ -18,7 +18,6 @@
#include <linux/pci.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
#include <asm/div64.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
...
...
@@ -507,32 +506,9 @@ early_param("video", early_video_setup);
*/
static
void
__init
p1022_ds_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
dma_addr_t
max
=
0xffffffff
;
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"p1022_ds_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_compatible_node
(
np
,
"pci"
,
"fsl,p1022-pcie"
)
{
struct
resource
rsrc
;
struct
pci_controller
*
hose
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
0x8000
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
hose
=
pci_find_hose_for_OF_device
(
np
);
max
=
min
(
max
,
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
);
}
#endif
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
diu_ops
.
get_pixel_format
=
p1022ds_get_pixel_format
;
diu_ops
.
set_gamma_table
=
p1022ds_set_gamma_table
;
...
...
@@ -601,18 +577,14 @@ static void __init p1022_ds_setup_arch(void)
mpc85xx_smp_init
();
#ifdef CONFIG_SWIOTLB
if
((
memblock_end_of_DRAM
()
-
1
)
>
max
)
{
ppc_swiotlb_enable
=
1
;
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
}
#endif
fsl_pci_assign_primary
();
swiotlb_detect_4g
();
pr_info
(
"Freescale P1022 DS reference board
\n
"
);
}
machine_
device
_initcall
(
p1022_ds
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1022_ds
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1022_ds
,
swiotlb_setup_bus_notifier
);
...
...
arch/powerpc/platforms/85xx/p1022_rdk.c
0 → 100644
浏览文件 @
caa1d631
/*
* P1022 RDK board specific routines
*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* Author: Timur Tabi <timur@freescale.com>
*
* Based on p1022_ds.c
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/pci.h>
#include <linux/of_platform.h>
#include <asm/div64.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <asm/udbg.h>
#include <asm/fsl_guts.h>
#include "smp.h"
#include "mpc85xx.h"
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
#define CLKDVDR_PXCKEN 0x80000000
#define CLKDVDR_PXCKINV 0x10000000
#define CLKDVDR_PXCKDLY 0x06000000
#define CLKDVDR_PXCLK_MASK 0x00FF0000
/**
* p1022rdk_set_monitor_port: switch the output to a different monitor port
*/
static
void
p1022rdk_set_monitor_port
(
enum
fsl_diu_monitor_port
port
)
{
if
(
port
!=
FSL_DIU_PORT_DVI
)
{
pr_err
(
"p1022rdk: unsupported monitor port %i
\n
"
,
port
);
return
;
}
}
/**
* p1022rdk_set_pixel_clock: program the DIU's clock
*
* @pixclock: the wavelength, in picoseconds, of the clock
*/
void
p1022rdk_set_pixel_clock
(
unsigned
int
pixclock
)
{
struct
device_node
*
guts_np
=
NULL
;
struct
ccsr_guts
__iomem
*
guts
;
unsigned
long
freq
;
u64
temp
;
u32
pxclk
;
/* Map the global utilities registers. */
guts_np
=
of_find_compatible_node
(
NULL
,
NULL
,
"fsl,p1022-guts"
);
if
(
!
guts_np
)
{
pr_err
(
"p1022rdk: missing global utilties device node
\n
"
);
return
;
}
guts
=
of_iomap
(
guts_np
,
0
);
of_node_put
(
guts_np
);
if
(
!
guts
)
{
pr_err
(
"p1022rdk: could not map global utilties device
\n
"
);
return
;
}
/* Convert pixclock from a wavelength to a frequency */
temp
=
1000000000000ULL
;
do_div
(
temp
,
pixclock
);
freq
=
temp
;
/*
* 'pxclk' is the ratio of the platform clock to the pixel clock.
* This number is programmed into the CLKDVDR register, and the valid
* range of values is 2-255.
*/
pxclk
=
DIV_ROUND_CLOSEST
(
fsl_get_sys_freq
(),
freq
);
pxclk
=
clamp_t
(
u32
,
pxclk
,
2
,
255
);
/* Disable the pixel clock, and set it to non-inverted and no delay */
clrbits32
(
&
guts
->
clkdvdr
,
CLKDVDR_PXCKEN
|
CLKDVDR_PXCKDLY
|
CLKDVDR_PXCLK_MASK
);
/* Enable the clock and set the pxclk */
setbits32
(
&
guts
->
clkdvdr
,
CLKDVDR_PXCKEN
|
(
pxclk
<<
16
));
iounmap
(
guts
);
}
/**
* p1022rdk_valid_monitor_port: set the monitor port for sysfs
*/
enum
fsl_diu_monitor_port
p1022rdk_valid_monitor_port
(
enum
fsl_diu_monitor_port
port
)
{
return
FSL_DIU_PORT_DVI
;
}
#endif
void
__init
p1022_rdk_pic_init
(
void
)
{
struct
mpic
*
mpic
=
mpic_alloc
(
NULL
,
0
,
MPIC_BIG_ENDIAN
|
MPIC_SINGLE_DEST_CPU
,
0
,
256
,
" OpenPIC "
);
BUG_ON
(
mpic
==
NULL
);
mpic_init
(
mpic
);
}
/*
* Setup the architecture
*/
static
void
__init
p1022_rdk_setup_arch
(
void
)
{
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"p1022_rdk_setup_arch()"
,
0
);
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
diu_ops
.
set_monitor_port
=
p1022rdk_set_monitor_port
;
diu_ops
.
set_pixel_clock
=
p1022rdk_set_pixel_clock
;
diu_ops
.
valid_monitor_port
=
p1022rdk_valid_monitor_port
;
#endif
mpc85xx_smp_init
();
fsl_pci_assign_primary
();
swiotlb_detect_4g
();
pr_info
(
"Freescale / iVeia P1022 RDK reference board
\n
"
);
}
machine_arch_initcall
(
p1022_rdk
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1022_rdk
,
swiotlb_setup_bus_notifier
);
/*
* Called very early, device-tree isn't unflattened
*/
static
int
__init
p1022_rdk_probe
(
void
)
{
unsigned
long
root
=
of_get_flat_dt_root
();
return
of_flat_dt_is_compatible
(
root
,
"fsl,p1022rdk"
);
}
define_machine
(
p1022_rdk
)
{
.
name
=
"P1022 RDK"
,
.
probe
=
p1022_rdk_probe
,
.
setup_arch
=
p1022_rdk_setup_arch
,
.
init_IRQ
=
p1022_rdk_pic_init
,
#ifdef CONFIG_PCI
.
pcibios_fixup_bus
=
fsl_pcibios_fixup_bus
,
#endif
.
get_irq
=
mpic_get_irq
,
.
restart
=
fsl_rstcr_restart
,
.
calibrate_decr
=
generic_calibrate_decr
,
.
progress
=
udbg_progress
,
};
arch/powerpc/platforms/85xx/p1023_rds.c
浏览文件 @
caa1d631
...
...
@@ -80,15 +80,12 @@ static void __init mpc85xx_rds_setup_arch(void)
}
}
#ifdef CONFIG_PCI
for_each_compatible_node
(
np
,
"pci"
,
"fsl,p1023-pcie"
)
fsl_add_bridge
(
np
,
0
);
#endif
mpc85xx_smp_init
();
fsl_pci_assign_primary
();
}
machine_
device
_initcall
(
p1023_rds
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
p1023_rds
,
mpc85xx_common_publish_devices
);
static
void
__init
mpc85xx_rds_pic_init
(
void
)
{
...
...
arch/powerpc/platforms/85xx/p2041_rdb.c
浏览文件 @
caa1d631
...
...
@@ -80,7 +80,7 @@ define_machine(p2041_rdb) {
.
power_save
=
e500_idle
,
};
machine_
device
_initcall
(
p2041_rdb
,
corenet_ds_publish_devices
);
machine_
arch
_initcall
(
p2041_rdb
,
corenet_ds_publish_devices
);
#ifdef CONFIG_SWIOTLB
machine_arch_initcall
(
p2041_rdb
,
swiotlb_setup_bus_notifier
);
...
...
arch/powerpc/platforms/85xx/p3041_ds.c
浏览文件 @
caa1d631
...
...
@@ -82,7 +82,7 @@ define_machine(p3041_ds) {
.
power_save
=
e500_idle
,
};
machine_
device
_initcall
(
p3041_ds
,
corenet_ds_publish_devices
);
machine_
arch
_initcall
(
p3041_ds
,
corenet_ds_publish_devices
);
#ifdef CONFIG_SWIOTLB
machine_arch_initcall
(
p3041_ds
,
swiotlb_setup_bus_notifier
);
...
...
arch/powerpc/platforms/85xx/p4080_ds.c
浏览文件 @
caa1d631
...
...
@@ -81,7 +81,7 @@ define_machine(p4080_ds) {
.
power_save
=
e500_idle
,
};
machine_
device
_initcall
(
p4080_ds
,
corenet_ds_publish_devices
);
machine_
arch
_initcall
(
p4080_ds
,
corenet_ds_publish_devices
);
#ifdef CONFIG_SWIOTLB
machine_arch_initcall
(
p4080_ds
,
swiotlb_setup_bus_notifier
);
#endif
arch/powerpc/platforms/85xx/p5020_ds.c
浏览文件 @
caa1d631
...
...
@@ -91,7 +91,7 @@ define_machine(p5020_ds) {
#endif
};
machine_
device
_initcall
(
p5020_ds
,
corenet_ds_publish_devices
);
machine_
arch
_initcall
(
p5020_ds
,
corenet_ds_publish_devices
);
#ifdef CONFIG_SWIOTLB
machine_arch_initcall
(
p5020_ds
,
swiotlb_setup_bus_notifier
);
...
...
arch/powerpc/platforms/85xx/p5040_ds.c
0 → 100644
浏览文件 @
caa1d631
/*
* P5040 DS Setup
*
* Copyright 2009-2010 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <asm/machdep.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <linux/of_fdt.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <asm/ehv_pic.h>
#include "corenet_ds.h"
/*
* Called very early, device-tree isn't unflattened
*/
static
int
__init
p5040_ds_probe
(
void
)
{
unsigned
long
root
=
of_get_flat_dt_root
();
#ifdef CONFIG_SMP
extern
struct
smp_ops_t
smp_85xx_ops
;
#endif
if
(
of_flat_dt_is_compatible
(
root
,
"fsl,P5040DS"
))
return
1
;
/* Check if we're running under the Freescale hypervisor */
if
(
of_flat_dt_is_compatible
(
root
,
"fsl,P5040DS-hv"
))
{
ppc_md
.
init_IRQ
=
ehv_pic_init
;
ppc_md
.
get_irq
=
ehv_pic_get_irq
;
ppc_md
.
restart
=
fsl_hv_restart
;
ppc_md
.
power_off
=
fsl_hv_halt
;
ppc_md
.
halt
=
fsl_hv_halt
;
#ifdef CONFIG_SMP
/*
* Disable the timebase sync operations because we can't write
* to the timebase registers under the hypervisor.
*/
smp_85xx_ops
.
give_timebase
=
NULL
;
smp_85xx_ops
.
take_timebase
=
NULL
;
#endif
return
1
;
}
return
0
;
}
define_machine
(
p5040_ds
)
{
.
name
=
"P5040 DS"
,
.
probe
=
p5040_ds_probe
,
.
setup_arch
=
corenet_ds_setup_arch
,
.
init_IRQ
=
corenet_ds_pic_init
,
#ifdef CONFIG_PCI
.
pcibios_fixup_bus
=
fsl_pcibios_fixup_bus
,
#endif
/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
#ifdef CONFIG_PPC64
.
get_irq
=
mpic_get_irq
,
#else
.
get_irq
=
mpic_get_coreint_irq
,
#endif
.
restart
=
fsl_rstcr_restart
,
.
calibrate_decr
=
generic_calibrate_decr
,
.
progress
=
udbg_progress
,
#ifdef CONFIG_PPC64
.
power_save
=
book3e_idle
,
#else
.
power_save
=
e500_idle
,
#endif
};
machine_arch_initcall
(
p5040_ds
,
corenet_ds_publish_devices
);
#ifdef CONFIG_SWIOTLB
machine_arch_initcall
(
p5040_ds
,
swiotlb_setup_bus_notifier
);
#endif
arch/powerpc/platforms/85xx/qemu_e500.c
浏览文件 @
caa1d631
...
...
@@ -41,7 +41,8 @@ static void __init qemu_e500_setup_arch(void)
{
ppc_md
.
progress
(
"qemu_e500_setup_arch()"
,
0
);
fsl_pci_init
();
fsl_pci_assign_primary
();
swiotlb_detect_4g
();
mpc85xx_smp_init
();
}
...
...
@@ -55,7 +56,7 @@ static int __init qemu_e500_probe(void)
return
!!
of_flat_dt_is_compatible
(
root
,
"fsl,qemu-e500"
);
}
machine_
device
_initcall
(
qemu_e500
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
qemu_e500
,
mpc85xx_common_publish_devices
);
define_machine
(
qemu_e500
)
{
.
name
=
"QEMU e500"
,
...
...
arch/powerpc/platforms/85xx/sbc8548.c
浏览文件 @
caa1d631
...
...
@@ -88,26 +88,11 @@ static int __init sbc8548_hw_rev(void)
*/
static
void
__init
sbc8548_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"sbc8548_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8540-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
))
{
struct
resource
rsrc
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
0x8000
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
}
}
#endif
fsl_pci_assign_primary
();
sbc_rev
=
sbc8548_hw_rev
();
}
...
...
@@ -128,7 +113,7 @@ static void sbc8548_show_cpuinfo(struct seq_file *m)
seq_printf
(
m
,
"PLL setting
\t
: 0x%x
\n
"
,
((
phid1
>>
24
)
&
0x3f
));
}
machine_
device
_initcall
(
sbc8548
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
sbc8548
,
mpc85xx_common_publish_devices
);
/*
* Called very early, device-tree isn't unflattened
...
...
arch/powerpc/platforms/85xx/smp.c
浏览文件 @
caa1d631
...
...
@@ -2,7 +2,7 @@
* Author: Andy Fleming <afleming@freescale.com>
* Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2006-2008, 2011 Freescale Semiconductor Inc.
* Copyright 2006-2008, 2011
-2012
Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
...
...
@@ -17,6 +17,7 @@
#include <linux/of.h>
#include <linux/kexec.h>
#include <linux/highmem.h>
#include <linux/cpu.h>
#include <asm/machdep.h>
#include <asm/pgtable.h>
...
...
@@ -24,33 +25,118 @@
#include <asm/mpic.h>
#include <asm/cacheflush.h>
#include <asm/dbell.h>
#include <asm/fsl_guts.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/mpic.h>
#include "smp.h"
extern
void
__early_start
(
void
);
#define BOOT_ENTRY_ADDR_UPPER 0
#define BOOT_ENTRY_ADDR_LOWER 1
#define BOOT_ENTRY_R3_UPPER 2
#define BOOT_ENTRY_R3_LOWER 3
#define BOOT_ENTRY_RESV 4
#define BOOT_ENTRY_PIR 5
#define BOOT_ENTRY_R6_UPPER 6
#define BOOT_ENTRY_R6_LOWER 7
#define NUM_BOOT_ENTRY 8
#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
static
int
__init
smp_85xx_kick_cpu
(
int
nr
)
struct
epapr_spin_table
{
u32
addr_h
;
u32
addr_l
;
u32
r3_h
;
u32
r3_l
;
u32
reserved
;
u32
pir
;
};
static
struct
ccsr_guts
__iomem
*
guts
;
static
u64
timebase
;
static
int
tb_req
;
static
int
tb_valid
;
static
void
mpc85xx_timebase_freeze
(
int
freeze
)
{
uint32_t
mask
;
mask
=
CCSR_GUTS_DEVDISR_TB0
|
CCSR_GUTS_DEVDISR_TB1
;
if
(
freeze
)
setbits32
(
&
guts
->
devdisr
,
mask
);
else
clrbits32
(
&
guts
->
devdisr
,
mask
);
in_be32
(
&
guts
->
devdisr
);
}
static
void
mpc85xx_give_timebase
(
void
)
{
unsigned
long
flags
;
local_irq_save
(
flags
);
while
(
!
tb_req
)
barrier
();
tb_req
=
0
;
mpc85xx_timebase_freeze
(
1
);
timebase
=
get_tb
();
mb
();
tb_valid
=
1
;
while
(
tb_valid
)
barrier
();
mpc85xx_timebase_freeze
(
0
);
local_irq_restore
(
flags
);
}
static
void
mpc85xx_take_timebase
(
void
)
{
unsigned
long
flags
;
local_irq_save
(
flags
);
tb_req
=
1
;
while
(
!
tb_valid
)
barrier
();
set_tb
(
timebase
>>
32
,
timebase
&
0xffffffff
);
isync
();
tb_valid
=
0
;
local_irq_restore
(
flags
);
}
#ifdef CONFIG_HOTPLUG_CPU
static
void
__cpuinit
smp_85xx_mach_cpu_die
(
void
)
{
unsigned
int
cpu
=
smp_processor_id
();
u32
tmp
;
local_irq_disable
();
idle_task_exit
();
generic_set_cpu_dead
(
cpu
);
mb
();
mtspr
(
SPRN_TCR
,
0
);
__flush_disable_L1
();
tmp
=
(
mfspr
(
SPRN_HID0
)
&
~
(
HID0_DOZE
|
HID0_SLEEP
))
|
HID0_NAP
;
mtspr
(
SPRN_HID0
,
tmp
);
isync
();
/* Enter NAP mode. */
tmp
=
mfmsr
();
tmp
|=
MSR_WE
;
mb
();
mtmsr
(
tmp
);
isync
();
while
(
1
)
;
}
#endif
static
int
__cpuinit
smp_85xx_kick_cpu
(
int
nr
)
{
unsigned
long
flags
;
const
u64
*
cpu_rel_addr
;
__iomem
u32
*
bptr_vaddr
;
__iomem
struct
epapr_spin_table
*
spin_table
;
struct
device_node
*
np
;
int
n
=
0
,
hw_cpu
=
get_hard_smp_processor_id
(
nr
);
int
hw_cpu
=
get_hard_smp_processor_id
(
nr
);
int
ioremappable
;
int
ret
=
0
;
WARN_ON
(
nr
<
0
||
nr
>=
NR_CPUS
);
WARN_ON
(
hw_cpu
<
0
||
hw_cpu
>=
NR_CPUS
);
...
...
@@ -75,46 +161,81 @@ smp_85xx_kick_cpu(int nr)
/* Map the spin table */
if
(
ioremappable
)
bptr_vaddr
=
ioremap
(
*
cpu_rel_addr
,
SIZE_BOOT_ENTRY
);
spin_table
=
ioremap
(
*
cpu_rel_addr
,
sizeof
(
struct
epapr_spin_table
));
else
bptr_vaddr
=
phys_to_virt
(
*
cpu_rel_addr
);
spin_table
=
phys_to_virt
(
*
cpu_rel_addr
);
local_irq_save
(
flags
);
out_be32
(
bptr_vaddr
+
BOOT_ENTRY_PIR
,
hw_cpu
);
#ifdef CONFIG_PPC32
out_be32
(
bptr_vaddr
+
BOOT_ENTRY_ADDR_LOWER
,
__pa
(
__early_start
));
#ifdef CONFIG_HOTPLUG_CPU
/* Corresponding to generic_set_cpu_dead() */
generic_set_cpu_up
(
nr
);
if
(
system_state
==
SYSTEM_RUNNING
)
{
out_be32
(
&
spin_table
->
addr_l
,
0
);
/*
* We don't set the BPTR register here since it already points
* to the boot page properly.
*/
mpic_reset_core
(
hw_cpu
);
/* wait until core is ready... */
if
(
!
spin_event_timeout
(
in_be32
(
&
spin_table
->
addr_l
)
==
1
,
10000
,
100
))
{
pr_err
(
"%s: timeout waiting for core %d to reset
\n
"
,
__func__
,
hw_cpu
);
ret
=
-
ENOENT
;
goto
out
;
}
/* clear the acknowledge status */
__secondary_hold_acknowledge
=
-
1
;
}
#endif
out_be32
(
&
spin_table
->
pir
,
hw_cpu
);
out_be32
(
&
spin_table
->
addr_l
,
__pa
(
__early_start
));
if
(
!
ioremappable
)
flush_dcache_range
((
ulong
)
bptr_vaddr
,
(
ulong
)(
bptr_vaddr
+
SIZE_BOOT_ENTRY
));
flush_dcache_range
((
ulong
)
spin_table
,
(
ulong
)
spin_table
+
sizeof
(
struct
epapr_spin_table
));
/* Wait a bit for the CPU to ack. */
while
((
__secondary_hold_acknowledge
!=
hw_cpu
)
&&
(
++
n
<
1000
))
mdelay
(
1
);
if
(
!
spin_event_timeout
(
__secondary_hold_acknowledge
==
hw_cpu
,
10000
,
100
))
{
pr_err
(
"%s: timeout waiting for core %d to ack
\n
"
,
__func__
,
hw_cpu
);
ret
=
-
ENOENT
;
goto
out
;
}
out:
#else
smp_generic_kick_cpu
(
nr
);
out_be64
((
u64
*
)(
bptr_vaddr
+
BOOT_ENTRY_ADDR_UPPER
),
__pa
((
u64
)
*
((
unsigned
long
long
*
)
generic_secondary_smp_init
)));
out_be32
(
&
spin_table
->
pir
,
hw_cpu
);
out_be64
((
u64
*
)(
&
spin_table
->
addr_h
),
__pa
((
u64
)
*
((
unsigned
long
long
*
)
generic_secondary_smp_init
)));
if
(
!
ioremappable
)
flush_dcache_range
((
ulong
)
bptr_vaddr
,
(
ulong
)(
bptr_vaddr
+
SIZE_BOOT_ENTRY
));
flush_dcache_range
((
ulong
)
spin_table
,
(
ulong
)
spin_table
+
sizeof
(
struct
epapr_spin_table
));
#endif
local_irq_restore
(
flags
);
if
(
ioremappable
)
iounmap
(
bptr_vaddr
);
pr_debug
(
"waited %d msecs for CPU #%d.
\n
"
,
n
,
nr
);
iounmap
(
spin_table
);
return
0
;
return
ret
;
}
struct
smp_ops_t
smp_85xx_ops
=
{
.
kick_cpu
=
smp_85xx_kick_cpu
,
#ifdef CONFIG_HOTPLUG_CPU
.
cpu_disable
=
generic_cpu_disable
,
.
cpu_die
=
generic_cpu_die
,
#endif
#ifdef CONFIG_KEXEC
.
give_timebase
=
smp_generic_give_timebase
,
.
take_timebase
=
smp_generic_take_timebase
,
...
...
@@ -218,8 +339,7 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
}
#endif
/* CONFIG_KEXEC */
static
void
__init
smp_85xx_setup_cpu
(
int
cpu_nr
)
static
void
__cpuinit
smp_85xx_setup_cpu
(
int
cpu_nr
)
{
if
(
smp_85xx_ops
.
probe
==
smp_mpic_probe
)
mpic_setup_this_cpu
();
...
...
@@ -228,6 +348,16 @@ smp_85xx_setup_cpu(int cpu_nr)
doorbell_setup_this_cpu
();
}
static
const
struct
of_device_id
mpc85xx_smp_guts_ids
[]
=
{
{
.
compatible
=
"fsl,mpc8572-guts"
,
},
{
.
compatible
=
"fsl,p1020-guts"
,
},
{
.
compatible
=
"fsl,p1021-guts"
,
},
{
.
compatible
=
"fsl,p1022-guts"
,
},
{
.
compatible
=
"fsl,p1023-guts"
,
},
{
.
compatible
=
"fsl,p2020-guts"
,
},
{},
};
void
__init
mpc85xx_smp_init
(
void
)
{
struct
device_node
*
np
;
...
...
@@ -249,6 +379,22 @@ void __init mpc85xx_smp_init(void)
smp_85xx_ops
.
cause_ipi
=
doorbell_cause_ipi
;
}
np
=
of_find_matching_node
(
NULL
,
mpc85xx_smp_guts_ids
);
if
(
np
)
{
guts
=
of_iomap
(
np
,
0
);
of_node_put
(
np
);
if
(
!
guts
)
{
pr_err
(
"%s: Could not map guts node address
\n
"
,
__func__
);
return
;
}
smp_85xx_ops
.
give_timebase
=
mpc85xx_give_timebase
;
smp_85xx_ops
.
take_timebase
=
mpc85xx_take_timebase
;
#ifdef CONFIG_HOTPLUG_CPU
ppc_md
.
cpu_die
=
smp_85xx_mach_cpu_die
;
#endif
}
smp_ops
=
&
smp_85xx_ops
;
#ifdef CONFIG_KEXEC
...
...
arch/powerpc/platforms/85xx/socrates.c
浏览文件 @
caa1d631
...
...
@@ -66,20 +66,13 @@ static void __init socrates_pic_init(void)
*/
static
void
__init
socrates_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"socrates_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_compatible_node
(
np
,
"pci"
,
"fsl,mpc8540-pci"
)
fsl_add_bridge
(
np
,
1
);
#endif
fsl_pci_assign_primary
();
}
machine_
device
_initcall
(
socrates
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
socrates
,
mpc85xx_common_publish_devices
);
/*
* Called very early, device-tree isn't unflattened
...
...
arch/powerpc/platforms/85xx/stx_gp3.c
浏览文件 @
caa1d631
...
...
@@ -60,21 +60,14 @@ static void __init stx_gp3_pic_init(void)
*/
static
void
__init
stx_gp3_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"stx_gp3_setup_arch()"
,
0
);
fsl_pci_assign_primary
();
#ifdef CONFIG_CPM2
cpm2_reset
();
#endif
#ifdef CONFIG_PCI
for_each_compatible_node
(
np
,
"pci"
,
"fsl,mpc8540-pci"
)
fsl_add_bridge
(
np
,
1
);
#endif
}
static
void
stx_gp3_show_cpuinfo
(
struct
seq_file
*
m
)
...
...
@@ -93,7 +86,7 @@ static void stx_gp3_show_cpuinfo(struct seq_file *m)
seq_printf
(
m
,
"PLL setting
\t
: 0x%x
\n
"
,
((
phid1
>>
24
)
&
0x3f
));
}
machine_
device
_initcall
(
stx_gp3
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
stx_gp3
,
mpc85xx_common_publish_devices
);
/*
* Called very early, device-tree isn't unflattened
...
...
arch/powerpc/platforms/85xx/tqm85xx.c
浏览文件 @
caa1d631
...
...
@@ -59,10 +59,6 @@ static void __init tqm85xx_pic_init(void)
*/
static
void
__init
tqm85xx_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"tqm85xx_setup_arch()"
,
0
);
...
...
@@ -70,20 +66,7 @@ static void __init tqm85xx_setup_arch(void)
cpm2_reset
();
#endif
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8540-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
))
{
struct
resource
rsrc
;
if
(
!
of_address_to_resource
(
np
,
0
,
&
rsrc
))
{
if
((
rsrc
.
start
&
0xfffff
)
==
0x8000
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
}
}
}
#endif
fsl_pci_assign_primary
();
}
static
void
tqm85xx_show_cpuinfo
(
struct
seq_file
*
m
)
...
...
@@ -123,7 +106,7 @@ static void __devinit tqm85xx_ti1520_fixup(struct pci_dev *pdev)
DECLARE_PCI_FIXUP_HEADER
(
PCI_VENDOR_ID_TI
,
PCI_DEVICE_ID_TI_1520
,
tqm85xx_ti1520_fixup
);
machine_
device
_initcall
(
tqm85xx
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
tqm85xx
,
mpc85xx_common_publish_devices
);
static
const
char
*
board
[]
__initdata
=
{
"tqc,tqm8540"
,
...
...
arch/powerpc/platforms/85xx/xes_mpc85xx.c
浏览文件 @
caa1d631
...
...
@@ -111,18 +111,11 @@ static void xes_mpc85xx_fixups(void)
}
}
#ifdef CONFIG_PCI
static
int
primary_phb_addr
;
#endif
/*
* Setup the architecture
*/
static
void
__init
xes_mpc85xx_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
struct
device_node
*
root
;
const
char
*
model
=
"Unknown"
;
...
...
@@ -137,26 +130,14 @@ static void __init xes_mpc85xx_setup_arch(void)
xes_mpc85xx_fixups
();
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8540-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8548-pcie"
))
{
struct
resource
rsrc
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
primary_phb_addr
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
}
}
#endif
mpc85xx_smp_init
();
fsl_pci_assign_primary
();
}
machine_
device
_initcall
(
xes_mpc8572
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
xes_mpc8548
,
mpc85xx_common_publish_devices
);
machine_
device
_initcall
(
xes_mpc8540
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
xes_mpc8572
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
xes_mpc8548
,
mpc85xx_common_publish_devices
);
machine_
arch
_initcall
(
xes_mpc8540
,
mpc85xx_common_publish_devices
);
/*
* Called very early, device-tree isn't unflattened
...
...
@@ -165,42 +146,21 @@ static int __init xes_mpc8572_probe(void)
{
unsigned
long
root
=
of_get_flat_dt_root
();
if
(
of_flat_dt_is_compatible
(
root
,
"xes,MPC8572"
))
{
#ifdef CONFIG_PCI
primary_phb_addr
=
0x8000
;
#endif
return
1
;
}
else
{
return
0
;
}
return
of_flat_dt_is_compatible
(
root
,
"xes,MPC8572"
);
}
static
int
__init
xes_mpc8548_probe
(
void
)
{
unsigned
long
root
=
of_get_flat_dt_root
();
if
(
of_flat_dt_is_compatible
(
root
,
"xes,MPC8548"
))
{
#ifdef CONFIG_PCI
primary_phb_addr
=
0xb000
;
#endif
return
1
;
}
else
{
return
0
;
}
return
of_flat_dt_is_compatible
(
root
,
"xes,MPC8548"
);
}
static
int
__init
xes_mpc8540_probe
(
void
)
{
unsigned
long
root
=
of_get_flat_dt_root
();
if
(
of_flat_dt_is_compatible
(
root
,
"xes,MPC8540"
))
{
#ifdef CONFIG_PCI
primary_phb_addr
=
0xb000
;
#endif
return
1
;
}
else
{
return
0
;
}
return
of_flat_dt_is_compatible
(
root
,
"xes,MPC8540"
);
}
define_machine
(
xes_mpc8572
)
{
...
...
arch/powerpc/platforms/86xx/gef_ppc9a.c
浏览文件 @
caa1d631
...
...
@@ -73,13 +73,6 @@ static void __init gef_ppc9a_init_irq(void)
static
void
__init
gef_ppc9a_setup_arch
(
void
)
{
struct
device_node
*
regs
;
#ifdef CONFIG_PCI
struct
device_node
*
np
;
for_each_compatible_node
(
np
,
"pci"
,
"fsl,mpc8641-pcie"
)
{
fsl_add_bridge
(
np
,
1
);
}
#endif
printk
(
KERN_INFO
"GE Intelligent Platforms PPC9A 6U VME SBC
\n
"
);
...
...
@@ -87,6 +80,8 @@ static void __init gef_ppc9a_setup_arch(void)
mpc86xx_smp_init
();
#endif
fsl_pci_assign_primary
();
/* Remap basic board registers */
regs
=
of_find_compatible_node
(
NULL
,
NULL
,
"gef,ppc9a-fpga-regs"
);
if
(
regs
)
{
...
...
@@ -221,6 +216,7 @@ static long __init mpc86xx_time_init(void)
static
__initdata
struct
of_device_id
of_bus_ids
[]
=
{
{
.
compatible
=
"simple-bus"
,
},
{
.
compatible
=
"gianfar"
,
},
{
.
compatible
=
"fsl,mpc8641-pcie"
,
},
{},
};
...
...
@@ -231,7 +227,7 @@ static int __init declare_of_platform_devices(void)
return
0
;
}
machine_
device
_initcall
(
gef_ppc9a
,
declare_of_platform_devices
);
machine_
arch
_initcall
(
gef_ppc9a
,
declare_of_platform_devices
);
define_machine
(
gef_ppc9a
)
{
.
name
=
"GE PPC9A"
,
...
...
arch/powerpc/platforms/86xx/gef_sbc310.c
浏览文件 @
caa1d631
...
...
@@ -73,20 +73,14 @@ static void __init gef_sbc310_init_irq(void)
static
void
__init
gef_sbc310_setup_arch
(
void
)
{
struct
device_node
*
regs
;
#ifdef CONFIG_PCI
struct
device_node
*
np
;
for_each_compatible_node
(
np
,
"pci"
,
"fsl,mpc8641-pcie"
)
{
fsl_add_bridge
(
np
,
1
);
}
#endif
printk
(
KERN_INFO
"GE Intelligent Platforms SBC310 6U VPX SBC
\n
"
);
#ifdef CONFIG_SMP
mpc86xx_smp_init
();
#endif
fsl_pci_assign_primary
();
/* Remap basic board registers */
regs
=
of_find_compatible_node
(
NULL
,
NULL
,
"gef,fpga-regs"
);
if
(
regs
)
{
...
...
@@ -209,6 +203,7 @@ static long __init mpc86xx_time_init(void)
static
__initdata
struct
of_device_id
of_bus_ids
[]
=
{
{
.
compatible
=
"simple-bus"
,
},
{
.
compatible
=
"gianfar"
,
},
{
.
compatible
=
"fsl,mpc8641-pcie"
,
},
{},
};
...
...
@@ -219,7 +214,7 @@ static int __init declare_of_platform_devices(void)
return
0
;
}
machine_
device
_initcall
(
gef_sbc310
,
declare_of_platform_devices
);
machine_
arch
_initcall
(
gef_sbc310
,
declare_of_platform_devices
);
define_machine
(
gef_sbc310
)
{
.
name
=
"GE SBC310"
,
...
...
arch/powerpc/platforms/86xx/gef_sbc610.c
浏览文件 @
caa1d631
...
...
@@ -73,13 +73,6 @@ static void __init gef_sbc610_init_irq(void)
static
void
__init
gef_sbc610_setup_arch
(
void
)
{
struct
device_node
*
regs
;
#ifdef CONFIG_PCI
struct
device_node
*
np
;
for_each_compatible_node
(
np
,
"pci"
,
"fsl,mpc8641-pcie"
)
{
fsl_add_bridge
(
np
,
1
);
}
#endif
printk
(
KERN_INFO
"GE Intelligent Platforms SBC610 6U VPX SBC
\n
"
);
...
...
@@ -87,6 +80,8 @@ static void __init gef_sbc610_setup_arch(void)
mpc86xx_smp_init
();
#endif
fsl_pci_assign_primary
();
/* Remap basic board registers */
regs
=
of_find_compatible_node
(
NULL
,
NULL
,
"gef,fpga-regs"
);
if
(
regs
)
{
...
...
@@ -198,6 +193,7 @@ static long __init mpc86xx_time_init(void)
static
__initdata
struct
of_device_id
of_bus_ids
[]
=
{
{
.
compatible
=
"simple-bus"
,
},
{
.
compatible
=
"gianfar"
,
},
{
.
compatible
=
"fsl,mpc8641-pcie"
,
},
{},
};
...
...
@@ -208,7 +204,7 @@ static int __init declare_of_platform_devices(void)
return
0
;
}
machine_
device
_initcall
(
gef_sbc610
,
declare_of_platform_devices
);
machine_
arch
_initcall
(
gef_sbc610
,
declare_of_platform_devices
);
define_machine
(
gef_sbc610
)
{
.
name
=
"GE SBC610"
,
...
...
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
浏览文件 @
caa1d631
...
...
@@ -91,6 +91,9 @@ static struct of_device_id __initdata mpc8610_ids[] = {
{
.
compatible
=
"simple-bus"
,
},
/* So that the DMA channel nodes can be probed individually: */
{
.
compatible
=
"fsl,eloplus-dma"
,
},
/* PCI controllers */
{
.
compatible
=
"fsl,mpc8610-pci"
,
},
{
.
compatible
=
"fsl,mpc8641-pcie"
,
},
{}
};
...
...
@@ -107,7 +110,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
return
0
;
}
machine_
device
_initcall
(
mpc86xx_hpcd
,
mpc8610_declare_of_platform_devices
);
machine_
arch
_initcall
(
mpc86xx_hpcd
,
mpc8610_declare_of_platform_devices
);
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
...
...
@@ -278,25 +281,13 @@ mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
static
void
__init
mpc86xx_hpcd_setup_arch
(
void
)
{
struct
resource
r
;
struct
device_node
*
np
;
unsigned
char
*
pixis
;
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"mpc86xx_hpcd_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_node_by_type
(
np
,
"pci"
)
{
if
(
of_device_is_compatible
(
np
,
"fsl,mpc8610-pci"
)
||
of_device_is_compatible
(
np
,
"fsl,mpc8641-pcie"
))
{
struct
resource
rsrc
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
0xa000
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
}
}
#endif
fsl_pci_assign_primary
();
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
diu_ops
.
get_pixel_format
=
mpc8610hpcd_get_pixel_format
;
diu_ops
.
set_gamma_table
=
mpc8610hpcd_set_gamma_table
;
...
...
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
浏览文件 @
caa1d631
...
...
@@ -19,7 +19,6 @@
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
#include <asm/time.h>
#include <asm/machdep.h>
...
...
@@ -51,15 +50,8 @@ extern int uli_exclude_device(struct pci_controller *hose,
static
int
mpc86xx_exclude_device
(
struct
pci_controller
*
hose
,
u_char
bus
,
u_char
devfn
)
{
struct
device_node
*
node
;
struct
resource
rsrc
;
node
=
hose
->
dn
;
of_address_to_resource
(
node
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
0x8000
)
{
if
(
hose
->
dn
==
fsl_pci_primary
)
return
uli_exclude_device
(
hose
,
bus
,
devfn
);
}
return
PCIBIOS_SUCCESSFUL
;
}
...
...
@@ -69,30 +61,11 @@ static int mpc86xx_exclude_device(struct pci_controller *hose,
static
void
__init
mpc86xx_hpcn_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
struct
pci_controller
*
hose
;
#endif
dma_addr_t
max
=
0xffffffff
;
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"mpc86xx_hpcn_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_compatible_node
(
np
,
"pci"
,
"fsl,mpc8641-pcie"
)
{
struct
resource
rsrc
;
of_address_to_resource
(
np
,
0
,
&
rsrc
);
if
((
rsrc
.
start
&
0xfffff
)
==
0x8000
)
fsl_add_bridge
(
np
,
1
);
else
fsl_add_bridge
(
np
,
0
);
hose
=
pci_find_hose_for_OF_device
(
np
);
max
=
min
(
max
,
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
);
}
ppc_md
.
pci_exclude_device
=
mpc86xx_exclude_device
;
#endif
printk
(
"MPC86xx HPCN board from Freescale Semiconductor
\n
"
);
...
...
@@ -101,13 +74,9 @@ mpc86xx_hpcn_setup_arch(void)
mpc86xx_smp_init
();
#endif
#ifdef CONFIG_SWIOTLB
if
((
memblock_end_of_DRAM
()
-
1
)
>
max
)
{
ppc_swiotlb_enable
=
1
;
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
}
#endif
fsl_pci_assign_primary
();
swiotlb_detect_4g
();
}
...
...
@@ -162,6 +131,7 @@ static __initdata struct of_device_id of_bus_ids[] = {
{
.
compatible
=
"simple-bus"
,
},
{
.
compatible
=
"fsl,srio"
,
},
{
.
compatible
=
"gianfar"
,
},
{
.
compatible
=
"fsl,mpc8641-pcie"
,
},
{},
};
...
...
@@ -171,7 +141,7 @@ static int __init declare_of_platform_devices(void)
return
0
;
}
machine_
device
_initcall
(
mpc86xx_hpcn
,
declare_of_platform_devices
);
machine_
arch
_initcall
(
mpc86xx_hpcn
,
declare_of_platform_devices
);
machine_arch_initcall
(
mpc86xx_hpcn
,
swiotlb_setup_bus_notifier
);
define_machine
(
mpc86xx_hpcn
)
{
...
...
arch/powerpc/platforms/86xx/sbc8641d.c
浏览文件 @
caa1d631
...
...
@@ -38,23 +38,16 @@
static
void
__init
sbc8641_setup_arch
(
void
)
{
#ifdef CONFIG_PCI
struct
device_node
*
np
;
#endif
if
(
ppc_md
.
progress
)
ppc_md
.
progress
(
"sbc8641_setup_arch()"
,
0
);
#ifdef CONFIG_PCI
for_each_compatible_node
(
np
,
"pci"
,
"fsl,mpc8641-pcie"
)
fsl_add_bridge
(
np
,
0
);
#endif
printk
(
"SBC8641 board from Wind River
\n
"
);
#ifdef CONFIG_SMP
mpc86xx_smp_init
();
#endif
fsl_pci_assign_primary
();
}
...
...
@@ -102,6 +95,7 @@ mpc86xx_time_init(void)
static
__initdata
struct
of_device_id
of_bus_ids
[]
=
{
{
.
compatible
=
"simple-bus"
,
},
{
.
compatible
=
"gianfar"
,
},
{
.
compatible
=
"fsl,mpc8641-pcie"
,
},
{},
};
...
...
@@ -111,7 +105,7 @@ static int __init declare_of_platform_devices(void)
return
0
;
}
machine_
device
_initcall
(
sbc8641
,
declare_of_platform_devices
);
machine_
arch
_initcall
(
sbc8641
,
declare_of_platform_devices
);
define_machine
(
sbc8641
)
{
.
name
=
"SBC8641D"
,
...
...
arch/powerpc/sysdev/Makefile
浏览文件 @
caa1d631
...
...
@@ -15,7 +15,7 @@ obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
obj-$(CONFIG_PPC_PMI)
+=
pmi.o
obj-$(CONFIG_U3_DART)
+=
dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM)
+=
mmio_nvram.o
obj-$(CONFIG_FSL_SOC)
+=
fsl_soc.o
obj-$(CONFIG_FSL_SOC)
+=
fsl_soc.o
fsl_mpic_err.o
obj-$(CONFIG_FSL_PCI)
+=
fsl_pci.o
$
(
fsl-msi-obj-y
)
obj-$(CONFIG_FSL_PMC)
+=
fsl_pmc.o
obj-$(CONFIG_FSL_LBC)
+=
fsl_lbc.o
...
...
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
浏览文件 @
caa1d631
...
...
@@ -193,6 +193,16 @@ static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
{
.
compatible
=
"fsl,mpc8548-l2-cache-controller"
,
},
{
.
compatible
=
"fsl,mpc8544-l2-cache-controller"
,},
{
.
compatible
=
"fsl,mpc8572-l2-cache-controller"
,},
{
.
compatible
=
"fsl,mpc8536-l2-cache-controller"
,},
{
.
compatible
=
"fsl,p1021-l2-cache-controller"
,},
{
.
compatible
=
"fsl,p1012-l2-cache-controller"
,},
{
.
compatible
=
"fsl,p1025-l2-cache-controller"
,},
{
.
compatible
=
"fsl,p1016-l2-cache-controller"
,},
{
.
compatible
=
"fsl,p1024-l2-cache-controller"
,},
{
.
compatible
=
"fsl,p1015-l2-cache-controller"
,},
{
.
compatible
=
"fsl,p1010-l2-cache-controller"
,},
{},
};
...
...
arch/powerpc/sysdev/fsl_mpic_err.c
0 → 100644
浏览文件 @
caa1d631
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* Author: Varun Sethi <varun.sethi@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2 of the
* License.
*
*/
#include <linux/irq.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mpic.h>
#include "mpic.h"
#define MPIC_ERR_INT_BASE 0x3900
#define MPIC_ERR_INT_EISR 0x0000
#define MPIC_ERR_INT_EIMR 0x0010
static
inline
u32
mpic_fsl_err_read
(
u32
__iomem
*
base
,
unsigned
int
err_reg
)
{
return
in_be32
(
base
+
(
err_reg
>>
2
));
}
static
inline
void
mpic_fsl_err_write
(
u32
__iomem
*
base
,
u32
value
)
{
out_be32
(
base
+
(
MPIC_ERR_INT_EIMR
>>
2
),
value
);
}
static
void
fsl_mpic_mask_err
(
struct
irq_data
*
d
)
{
u32
eimr
;
struct
mpic
*
mpic
=
irq_data_get_irq_chip_data
(
d
);
unsigned
int
src
=
virq_to_hw
(
d
->
irq
)
-
mpic
->
err_int_vecs
[
0
];
eimr
=
mpic_fsl_err_read
(
mpic
->
err_regs
,
MPIC_ERR_INT_EIMR
);
eimr
|=
(
1
<<
(
31
-
src
));
mpic_fsl_err_write
(
mpic
->
err_regs
,
eimr
);
}
static
void
fsl_mpic_unmask_err
(
struct
irq_data
*
d
)
{
u32
eimr
;
struct
mpic
*
mpic
=
irq_data_get_irq_chip_data
(
d
);
unsigned
int
src
=
virq_to_hw
(
d
->
irq
)
-
mpic
->
err_int_vecs
[
0
];
eimr
=
mpic_fsl_err_read
(
mpic
->
err_regs
,
MPIC_ERR_INT_EIMR
);
eimr
&=
~
(
1
<<
(
31
-
src
));
mpic_fsl_err_write
(
mpic
->
err_regs
,
eimr
);
}
static
struct
irq_chip
fsl_mpic_err_chip
=
{
.
irq_disable
=
fsl_mpic_mask_err
,
.
irq_mask
=
fsl_mpic_mask_err
,
.
irq_unmask
=
fsl_mpic_unmask_err
,
};
int
mpic_setup_error_int
(
struct
mpic
*
mpic
,
int
intvec
)
{
int
i
;
mpic
->
err_regs
=
ioremap
(
mpic
->
paddr
+
MPIC_ERR_INT_BASE
,
0x1000
);
if
(
!
mpic
->
err_regs
)
{
pr_err
(
"could not map mpic error registers
\n
"
);
return
-
ENOMEM
;
}
mpic
->
hc_err
=
fsl_mpic_err_chip
;
mpic
->
hc_err
.
name
=
mpic
->
name
;
mpic
->
flags
|=
MPIC_FSL_HAS_EIMR
;
/* allocate interrupt vectors for error interrupts */
for
(
i
=
MPIC_MAX_ERR
-
1
;
i
>=
0
;
i
--
)
mpic
->
err_int_vecs
[
i
]
=
--
intvec
;
return
0
;
}
int
mpic_map_error_int
(
struct
mpic
*
mpic
,
unsigned
int
virq
,
irq_hw_number_t
hw
)
{
if
((
mpic
->
flags
&
MPIC_FSL_HAS_EIMR
)
&&
(
hw
>=
mpic
->
err_int_vecs
[
0
]
&&
hw
<=
mpic
->
err_int_vecs
[
MPIC_MAX_ERR
-
1
]))
{
WARN_ON
(
mpic
->
flags
&
MPIC_SECONDARY
);
pr_debug
(
"mpic: mapping as Error Interrupt
\n
"
);
irq_set_chip_data
(
virq
,
mpic
);
irq_set_chip_and_handler
(
virq
,
&
mpic
->
hc_err
,
handle_level_irq
);
return
1
;
}
return
0
;
}
static
irqreturn_t
fsl_error_int_handler
(
int
irq
,
void
*
data
)
{
struct
mpic
*
mpic
=
(
struct
mpic
*
)
data
;
u32
eisr
,
eimr
;
int
errint
;
unsigned
int
cascade_irq
;
eisr
=
mpic_fsl_err_read
(
mpic
->
err_regs
,
MPIC_ERR_INT_EISR
);
eimr
=
mpic_fsl_err_read
(
mpic
->
err_regs
,
MPIC_ERR_INT_EIMR
);
if
(
!
(
eisr
&
~
eimr
))
return
IRQ_NONE
;
while
(
eisr
)
{
errint
=
__builtin_clz
(
eisr
);
cascade_irq
=
irq_linear_revmap
(
mpic
->
irqhost
,
mpic
->
err_int_vecs
[
errint
]);
WARN_ON
(
cascade_irq
==
NO_IRQ
);
if
(
cascade_irq
!=
NO_IRQ
)
{
generic_handle_irq
(
cascade_irq
);
}
else
{
eimr
|=
1
<<
(
31
-
errint
);
mpic_fsl_err_write
(
mpic
->
err_regs
,
eimr
);
}
eisr
&=
~
(
1
<<
(
31
-
errint
));
}
return
IRQ_HANDLED
;
}
void
mpic_err_int_init
(
struct
mpic
*
mpic
,
irq_hw_number_t
irqnum
)
{
unsigned
int
virq
;
int
ret
;
virq
=
irq_create_mapping
(
mpic
->
irqhost
,
irqnum
);
if
(
virq
==
NO_IRQ
)
{
pr_err
(
"Error interrupt setup failed
\n
"
);
return
;
}
/* Mask all error interrupts */
mpic_fsl_err_write
(
mpic
->
err_regs
,
~
0
);
ret
=
request_irq
(
virq
,
fsl_error_int_handler
,
IRQF_NO_THREAD
,
"mpic-error-int"
,
mpic
);
if
(
ret
)
pr_err
(
"Failed to register error interrupt handler
\n
"
);
}
arch/powerpc/sysdev/fsl_pci.c
浏览文件 @
caa1d631
...
...
@@ -143,18 +143,20 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
pr_debug
(
"PCI memory map start 0x%016llx, size 0x%016llx
\n
"
,
(
u64
)
rsrc
->
start
,
(
u64
)
resource_size
(
rsrc
));
if
(
of_device_is_compatible
(
hose
->
dn
,
"fsl,qoriq-pcie-v2.2"
))
{
win_idx
=
2
;
start_idx
=
0
;
end_idx
=
3
;
}
pci
=
ioremap
(
rsrc
->
start
,
resource_size
(
rsrc
));
if
(
!
pci
)
{
dev_err
(
hose
->
parent
,
"Unable to map ATMU registers
\n
"
);
return
;
}
if
(
early_find_capability
(
hose
,
0
,
0
,
PCI_CAP_ID_EXP
))
{
if
(
in_be32
(
&
pci
->
block_rev1
)
>=
PCIE_IP_REV_2_2
)
{
win_idx
=
2
;
start_idx
=
0
;
end_idx
=
3
;
}
}
/* Disable all windows (except powar0 since it's ignored) */
for
(
i
=
1
;
i
<
5
;
i
++
)
out_be32
(
&
pci
->
pow
[
i
].
powar
,
0
);
...
...
@@ -818,6 +820,7 @@ static const struct of_device_id pci_ids[] = {
{
.
compatible
=
"fsl,p1010-pcie"
,
},
{
.
compatible
=
"fsl,p1023-pcie"
,
},
{
.
compatible
=
"fsl,p4080-pcie"
,
},
{
.
compatible
=
"fsl,qoriq-pcie-v2.4"
,
},
{
.
compatible
=
"fsl,qoriq-pcie-v2.3"
,
},
{
.
compatible
=
"fsl,qoriq-pcie-v2.2"
,
},
{},
...
...
@@ -825,57 +828,78 @@ static const struct of_device_id pci_ids[] = {
struct
device_node
*
fsl_pci_primary
;
void
__devinit
fsl_pci_init
(
void
)
void
fsl_pci_assign_primary
(
void
)
{
int
ret
;
struct
device_node
*
node
;
struct
pci_controller
*
hose
;
dma_addr_t
max
=
0xffffffff
;
struct
device_node
*
np
;
/* Callers can specify the primary bus using other means. */
if
(
!
fsl_pci_primary
)
{
/* If a PCI host bridge contains an ISA node, it's primary. */
node
=
of_find_node_by_type
(
NULL
,
"isa"
);
while
((
fsl_pci_primary
=
of_get_parent
(
node
)))
{
of_node_put
(
node
);
node
=
fsl_pci_primary
;
if
(
of_match_node
(
pci_ids
,
node
))
break
;
}
if
(
fsl_pci_primary
)
return
;
/* If a PCI host bridge contains an ISA node, it's primary. */
np
=
of_find_node_by_type
(
NULL
,
"isa"
);
while
((
fsl_pci_primary
=
of_get_parent
(
np
)))
{
of_node_put
(
np
);
np
=
fsl_pci_primary
;
if
(
of_match_node
(
pci_ids
,
np
)
&&
of_device_is_available
(
np
))
return
;
}
node
=
NULL
;
for_each_node_by_type
(
node
,
"pci"
)
{
if
(
of_match_node
(
pci_ids
,
node
))
{
/*
* If there's no PCI host bridge with ISA, arbitrarily
* designate one as primary. This can go away once
* various bugs with primary-less systems are fixed.
*/
if
(
!
fsl_pci_primary
)
fsl_pci_primary
=
node
;
ret
=
fsl_add_bridge
(
node
,
fsl_pci_primary
==
node
);
if
(
ret
==
0
)
{
hose
=
pci_find_hose_for_OF_device
(
node
);
max
=
min
(
max
,
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
);
}
/*
* If there's no PCI host bridge with ISA, arbitrarily
* designate one as primary. This can go away once
* various bugs with primary-less systems are fixed.
*/
for_each_matching_node
(
np
,
pci_ids
)
{
if
(
of_device_is_available
(
np
))
{
fsl_pci_primary
=
np
;
of_node_put
(
np
);
return
;
}
}
}
static
int
__devinit
fsl_pci_probe
(
struct
platform_device
*
pdev
)
{
int
ret
;
struct
device_node
*
node
;
struct
pci_controller
*
hose
;
node
=
pdev
->
dev
.
of_node
;
ret
=
fsl_add_bridge
(
node
,
fsl_pci_primary
==
node
);
#ifdef CONFIG_SWIOTLB
/*
* if we couldn't map all of DRAM via the dma windows
* we need SWIOTLB to handle buffers located outside of
* dma capable memory region
*/
if
(
memblock_end_of_DRAM
()
-
1
>
max
)
{
ppc_swiotlb_enable
=
1
;
set_pci_dma_ops
(
&
swiotlb_dma_ops
);
ppc_md
.
pci_dma_dev_setup
=
pci_dma_dev_setup_swiotlb
;
if
(
ret
==
0
)
{
hose
=
pci_find_hose_for_OF_device
(
pdev
->
dev
.
of_node
);
/*
* if we couldn't map all of DRAM via the dma windows
* we need SWIOTLB to handle buffers located outside of
* dma capable memory region
*/
if
(
memblock_end_of_DRAM
()
-
1
>
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
)
ppc_swiotlb_enable
=
1
;
}
#endif
mpc85xx_pci_err_probe
(
pdev
);
return
0
;
}
static
struct
platform_driver
fsl_pci_driver
=
{
.
driver
=
{
.
name
=
"fsl-pci"
,
.
of_match_table
=
pci_ids
,
},
.
probe
=
fsl_pci_probe
,
};
static
int
__init
fsl_pci_init
(
void
)
{
return
platform_driver_register
(
&
fsl_pci_driver
);
}
arch_initcall
(
fsl_pci_init
);
#endif
arch/powerpc/sysdev/fsl_pci.h
浏览文件 @
caa1d631
...
...
@@ -16,6 +16,7 @@
#define PCIE_LTSSM 0x0404
/* PCIE Link Training and Status */
#define PCIE_LTSSM_L0 0x16
/* L0 state */
#define PCIE_IP_REV_2_2 0x02080202
/* PCIE IP block version Rev2.2 */
#define PIWAR_EN 0x80000000
/* Enable */
#define PIWAR_PF 0x20000000
/* prefetch */
#define PIWAR_TGI_LOCAL 0x00f00000
/* target - local memory */
...
...
@@ -57,7 +58,9 @@ struct ccsr_pci {
__be32
pex_pme_mes_disr
;
/* 0x.024 - PCIE PME and message disable register */
__be32
pex_pme_mes_ier
;
/* 0x.028 - PCIE PME and message interrupt enable register */
__be32
pex_pmcr
;
/* 0x.02c - PCIE power management command register */
u8
res3
[
3024
];
u8
res3
[
3016
];
__be32
block_rev1
;
/* 0x.bf8 - PCIE Block Revision register 1 */
__be32
block_rev2
;
/* 0x.bfc - PCIE Block Revision register 2 */
/* PCI/PCI Express outbound window 0-4
* Window 0 is the default window and is the only window enabled upon reset.
...
...
@@ -95,10 +98,19 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose);
extern
struct
device_node
*
fsl_pci_primary
;
#ifdef CONFIG_
FSL_
PCI
void
fsl_pci_
init
(
void
);
#ifdef CONFIG_PCI
void
fsl_pci_
assign_primary
(
void
);
#else
static
inline
void
fsl_pci_init
(
void
)
{}
static
inline
void
fsl_pci_assign_primary
(
void
)
{}
#endif
#ifdef CONFIG_EDAC_MPC85XX
int
mpc85xx_pci_err_probe
(
struct
platform_device
*
op
);
#else
static
inline
int
mpc85xx_pci_err_probe
(
struct
platform_device
*
op
)
{
return
-
ENOTSUPP
;
}
#endif
#endif
/* __POWERPC_FSL_PCI_H */
...
...
arch/powerpc/sysdev/mpic.c
浏览文件 @
caa1d631
...
...
@@ -6,7 +6,7 @@
* with various broken implementations of this HW.
*
* Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
* Copyright 2010-201
1
Freescale Semiconductor, Inc.
* Copyright 2010-201
2
Freescale Semiconductor, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
...
...
@@ -221,24 +221,24 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu
_mpic_write
(
mpic
->
reg_type
,
&
mpic
->
gregs
,
offset
,
value
);
}
static
inline
u
32
_mpic_tm_read
(
struct
mpic
*
mpic
,
unsigned
int
tm
)
static
inline
u
nsigned
int
mpic_tm_offset
(
struct
mpic
*
mpic
,
unsigned
int
tm
)
{
unsigned
int
offset
=
MPIC_INFO
(
TIMER_VECTOR_PRI
)
+
((
tm
&
3
)
*
MPIC_INFO
(
TIMER_STRIDE
));
return
(
tm
>>
2
)
*
MPIC_TIMER_GROUP_STRIDE
+
(
tm
&
3
)
*
MPIC_INFO
(
TIMER_STRIDE
);
}
if
(
tm
>=
4
)
offset
+=
0x1000
/
4
;
static
inline
u32
_mpic_tm_read
(
struct
mpic
*
mpic
,
unsigned
int
tm
)
{
unsigned
int
offset
=
mpic_tm_offset
(
mpic
,
tm
)
+
MPIC_INFO
(
TIMER_VECTOR_PRI
);
return
_mpic_read
(
mpic
->
reg_type
,
&
mpic
->
tmregs
,
offset
);
}
static
inline
void
_mpic_tm_write
(
struct
mpic
*
mpic
,
unsigned
int
tm
,
u32
value
)
{
unsigned
int
offset
=
MPIC_INFO
(
TIMER_VECTOR_PRI
)
+
((
tm
&
3
)
*
MPIC_INFO
(
TIMER_STRIDE
));
if
(
tm
>=
4
)
offset
+=
0x1000
/
4
;
unsigned
int
offset
=
mpic_tm_offset
(
mpic
,
tm
)
+
MPIC_INFO
(
TIMER_VECTOR_PRI
);
_mpic_write
(
mpic
->
reg_type
,
&
mpic
->
tmregs
,
offset
,
value
);
}
...
...
@@ -1026,6 +1026,9 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
return
0
;
}
if
(
mpic_map_error_int
(
mpic
,
virq
,
hw
))
return
0
;
if
(
hw
>=
mpic
->
num_sources
)
return
-
EINVAL
;
...
...
@@ -1085,7 +1088,16 @@ static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
*/
switch
(
intspec
[
2
])
{
case
0
:
case
1
:
/* no EISR/EIMR support for now, treat as shared IRQ */
break
;
case
1
:
if
(
!
(
mpic
->
flags
&
MPIC_FSL_HAS_EIMR
))
break
;
if
(
intspec
[
3
]
>=
ARRAY_SIZE
(
mpic
->
err_int_vecs
))
return
-
EINVAL
;
*
out_hwirq
=
mpic
->
err_int_vecs
[
intspec
[
3
]];
break
;
case
2
:
if
(
intspec
[
0
]
>=
ARRAY_SIZE
(
mpic
->
ipi_vecs
))
...
...
@@ -1301,6 +1313,42 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map
(
mpic
,
mpic
->
paddr
,
&
mpic
->
gregs
,
MPIC_INFO
(
GREG_BASE
),
0x1000
);
mpic_map
(
mpic
,
mpic
->
paddr
,
&
mpic
->
tmregs
,
MPIC_INFO
(
TIMER_BASE
),
0x1000
);
if
(
mpic
->
flags
&
MPIC_FSL
)
{
u32
brr1
,
version
;
int
ret
;
/*
* Yes, Freescale really did put global registers in the
* magic per-cpu area -- and they don't even show up in the
* non-magic per-cpu copies that this driver normally uses.
*/
mpic_map
(
mpic
,
mpic
->
paddr
,
&
mpic
->
thiscpuregs
,
MPIC_CPU_THISBASE
,
0x1000
);
brr1
=
_mpic_read
(
mpic
->
reg_type
,
&
mpic
->
thiscpuregs
,
MPIC_FSL_BRR1
);
version
=
brr1
&
MPIC_FSL_BRR1_VER
;
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR
* was added in MPIC version 4.1.
*
* Over here we reserve vector number space for error
* interrupt vectors. This space is stolen from the
* global vector number space, as in case of ipis
* and timer interrupts.
*
* Available vector space = intvec_top - 12, where 12
* is the number of vectors which have been consumed by
* ipis and timer interrupts.
*/
if
(
version
>=
0x401
)
{
ret
=
mpic_setup_error_int
(
mpic
,
intvec_top
-
12
);
if
(
ret
)
return
NULL
;
}
}
/* Reset */
/* When using a device-node, reset requests are only honored if the MPIC
...
...
@@ -1440,6 +1488,7 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
void
__init
mpic_init
(
struct
mpic
*
mpic
)
{
int
i
,
cpu
;
int
num_timers
=
4
;
BUG_ON
(
mpic
->
num_sources
==
0
);
...
...
@@ -1448,15 +1497,34 @@ void __init mpic_init(struct mpic *mpic)
/* Set current processor priority to max */
mpic_cpu_write
(
MPIC_INFO
(
CPU_CURRENT_TASK_PRI
),
0xf
);
if
(
mpic
->
flags
&
MPIC_FSL
)
{
u32
brr1
=
_mpic_read
(
mpic
->
reg_type
,
&
mpic
->
thiscpuregs
,
MPIC_FSL_BRR1
);
u32
version
=
brr1
&
MPIC_FSL_BRR1_VER
;
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
* mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
* I don't know about the status of intermediate versions (or
* whether they even exist).
*/
if
(
version
>=
0x0301
)
num_timers
=
8
;
}
/* FSL mpic error interrupt intialization */
if
(
mpic
->
flags
&
MPIC_FSL_HAS_EIMR
)
mpic_err_int_init
(
mpic
,
MPIC_FSL_ERR_INT
);
/* Initialize timers to our reserved vectors and mask them for now */
for
(
i
=
0
;
i
<
4
;
i
++
)
{
for
(
i
=
0
;
i
<
num_timers
;
i
++
)
{
unsigned
int
offset
=
mpic_tm_offset
(
mpic
,
i
);
mpic_write
(
mpic
->
tmregs
,
i
*
MPIC_INFO
(
TIMER_STRIDE
)
+
MPIC_INFO
(
TIMER_DESTINATION
),
offset
+
MPIC_INFO
(
TIMER_DESTINATION
),
1
<<
hard_smp_processor_id
());
mpic_write
(
mpic
->
tmregs
,
i
*
MPIC_INFO
(
TIMER_STRIDE
)
+
MPIC_INFO
(
TIMER_VECTOR_PRI
),
offset
+
MPIC_INFO
(
TIMER_VECTOR_PRI
),
MPIC_VECPRI_MASK
|
(
9
<<
MPIC_VECPRI_PRIORITY_SHIFT
)
|
(
mpic
->
timer_vecs
[
0
]
+
i
));
...
...
arch/powerpc/sysdev/mpic.h
浏览文件 @
caa1d631
...
...
@@ -40,4 +40,26 @@ extern int mpic_set_affinity(struct irq_data *d,
const
struct
cpumask
*
cpumask
,
bool
force
);
extern
void
mpic_reset_core
(
int
cpu
);
#ifdef CONFIG_FSL_SOC
extern
int
mpic_map_error_int
(
struct
mpic
*
mpic
,
unsigned
int
virq
,
irq_hw_number_t
hw
);
extern
void
mpic_err_int_init
(
struct
mpic
*
mpic
,
irq_hw_number_t
irqnum
);
extern
int
mpic_setup_error_int
(
struct
mpic
*
mpic
,
int
intvec
);
#else
static
inline
int
mpic_map_error_int
(
struct
mpic
*
mpic
,
unsigned
int
virq
,
irq_hw_number_t
hw
)
{
return
0
;
}
static
inline
void
mpic_err_int_init
(
struct
mpic
*
mpic
,
irq_hw_number_t
irqnum
)
{
return
;
}
static
inline
int
mpic_setup_error_int
(
struct
mpic
*
mpic
,
int
intvec
)
{
return
-
1
;
}
#endif
#endif
/* _POWERPC_SYSDEV_MPIC_H */
drivers/edac/mpc85xx_edac.c
浏览文件 @
caa1d631
此差异已折叠。
点击以展开。
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录