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提交 c7ed1ab3 编写于 作者: P Paul Mundt
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serial: sh-sci: clkdev updates for MSTP gating. 

This fixes up some of the I/D/F clock ambiguity in the sh-sci driver.
The interface clock in most cases just wraps back to the peripheral
clock, while the function clock wraps in to the MSTP bits. As the logic
was somewhat inverted, this cleans that up, and also enables all CPUs
with SCI MSTP bits to match function clocks through clkdev lookup.

As a result, this gets rid of the clk string abuse on the sh side, and
the clock string will be killed off once the ARM code has had a chance to
sync up. This also enables MSTP gating on CPUs like 7786 which had never
wired it up before. Impacted CPUs are primarily all SH-Mobiles, SH7785,
and SH7786.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
上级 d28c145d
隐藏空白更改
内联 并排
Showing with 71 addition and 80 deletion
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
浏览文件 @ c7ed1ab3
...@@ -159,10 +159,10 @@ static struct clk mstp_clks[] = { ...@@ -159,10 +159,10 @@ static struct clk mstp_clks[] = {
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0), SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
......
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
浏览文件 @ c7ed1ab3
...@@ -163,9 +163,9 @@ static struct clk mstp_clks[] = { ...@@ -163,9 +163,9 @@ static struct clk mstp_clks[] = {
MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0),
MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0),
MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
......
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
浏览文件 @ c7ed1ab3
...@@ -164,9 +164,9 @@ static struct clk mstp_clks[] = { ...@@ -164,9 +164,9 @@ static struct clk mstp_clks[] = {
SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
......
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
浏览文件 @ c7ed1ab3
...@@ -177,12 +177,12 @@ static struct clk mstp_clks[] = { ...@@ -177,12 +177,12 @@ static struct clk mstp_clks[] = {
SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), SH_HWBLK_CLK("sci_fck", 3, B_CLK, HWBLK_SCIF3, 0),
SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), SH_HWBLK_CLK("sci_fck", 4, B_CLK, HWBLK_SCIF4, 0),
SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), SH_HWBLK_CLK("sci_fck", 5, B_CLK, HWBLK_SCIF5, 0),
SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0), SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
......
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
浏览文件 @ c7ed1ab3
...@@ -194,12 +194,12 @@ static struct clk mstp_clks[] = { ...@@ -194,12 +194,12 @@ static struct clk mstp_clks[] = {
SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), SH_HWBLK_CLK("sci_fck", 3, B_CLK, HWBLK_SCIF3, 0),
SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), SH_HWBLK_CLK("sci_fck", 4, B_CLK, HWBLK_SCIF4, 0),
SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), SH_HWBLK_CLK("sci_fck", 5, B_CLK, HWBLK_SCIF5, 0),
SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
......
arch/sh/kernel/cpu/sh4a/clock-sh7785.c
浏览文件 @ c7ed1ab3
...@@ -88,12 +88,12 @@ struct clk div4_clks[DIV4_NR] = { ...@@ -88,12 +88,12 @@ struct clk div4_clks[DIV4_NR] = {
static struct clk mstp_clks[] = { static struct clk mstp_clks[] = {
/* MSTPCR0 */ /* MSTPCR0 */
SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
......
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
浏览文件 @ c7ed1ab3
...@@ -87,12 +87,12 @@ struct clk div4_clks[DIV4_NR] = { ...@@ -87,12 +87,12 @@ struct clk div4_clks[DIV4_NR] = {
static struct clk mstp_clks[] = { static struct clk mstp_clks[] = {
/* MSTPCR0 */ /* MSTPCR0 */
SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
......
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
浏览文件 @ c7ed1ab3
...@@ -21,7 +21,6 @@ static struct plat_sci_port scif0_platform_data = { ...@@ -21,7 +21,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0",
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
...@@ -37,7 +36,6 @@ static struct plat_sci_port scif1_platform_data = { ...@@ -37,7 +36,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
.clk = "scif1",
}; };
static struct platform_device scif1_device = { static struct platform_device scif1_device = {
...@@ -53,7 +51,6 @@ static struct plat_sci_port scif2_platform_data = { ...@@ -53,7 +51,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { 82, 82, 82, 82 },
.clk = "scif2",
}; };
static struct platform_device scif2_device = { static struct platform_device scif2_device = {
...@@ -69,7 +66,6 @@ static struct plat_sci_port scif3_platform_data = { ...@@ -69,7 +66,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 83, 83, 83, 83 }, .irqs = { 83, 83, 83, 83 },
.clk = "scif3",
}; };
static struct platform_device scif3_device = { static struct platform_device scif3_device = {
......
arch/sh/kernel/cpu/sh4a/setup-sh7366.c
浏览文件 @ c7ed1ab3
...@@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = { ...@@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0",
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
......
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
浏览文件 @ c7ed1ab3
...@@ -174,7 +174,6 @@ static struct plat_sci_port scif0_platform_data = { ...@@ -174,7 +174,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0",
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
...@@ -190,7 +189,6 @@ static struct plat_sci_port scif1_platform_data = { ...@@ -190,7 +189,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
.clk = "scif1",
}; };
static struct platform_device scif1_device = { static struct platform_device scif1_device = {
...@@ -206,7 +204,6 @@ static struct plat_sci_port scif2_platform_data = { ...@@ -206,7 +204,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { 82, 82, 82, 82 },
.clk = "scif2",
}; };
static struct platform_device scif2_device = { static struct platform_device scif2_device = {
......
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
浏览文件 @ c7ed1ab3
...@@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = { ...@@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0",
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
...@@ -42,7 +41,6 @@ static struct plat_sci_port scif1_platform_data = { ...@@ -42,7 +41,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
.clk = "scif1",
}; };
static struct platform_device scif1_device = { static struct platform_device scif1_device = {
...@@ -58,7 +56,6 @@ static struct plat_sci_port scif2_platform_data = { ...@@ -58,7 +56,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { 82, 82, 82, 82 },
.clk = "scif2",
}; };
static struct platform_device scif2_device = { static struct platform_device scif2_device = {
...@@ -74,7 +71,6 @@ static struct plat_sci_port scif3_platform_data = { ...@@ -74,7 +71,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 56, 56, 56, 56 }, .irqs = { 56, 56, 56, 56 },
.clk = "scif3",
}; };
static struct platform_device scif3_device = { static struct platform_device scif3_device = {
...@@ -90,7 +86,6 @@ static struct plat_sci_port scif4_platform_data = { ...@@ -90,7 +86,6 @@ static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 88, 88, 88, 88 }, .irqs = { 88, 88, 88, 88 },
.clk = "scif4",
}; };
static struct platform_device scif4_device = { static struct platform_device scif4_device = {
...@@ -106,7 +101,6 @@ static struct plat_sci_port scif5_platform_data = { ...@@ -106,7 +101,6 @@ static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 109, 109, 109, 109 }, .irqs = { 109, 109, 109, 109 },
.clk = "scif5",
}; };
static struct platform_device scif5_device = { static struct platform_device scif5_device = {
......
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
浏览文件 @ c7ed1ab3
...@@ -213,7 +213,6 @@ static struct plat_sci_port scif0_platform_data = { ...@@ -213,7 +213,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 }, .irqs = { 80, 80, 80, 80 },
.clk = "scif0",
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
...@@ -229,7 +228,6 @@ static struct plat_sci_port scif1_platform_data = { ...@@ -229,7 +228,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 }, .irqs = { 81, 81, 81, 81 },
.clk = "scif1",
}; };
static struct platform_device scif1_device = { static struct platform_device scif1_device = {
...@@ -245,7 +243,6 @@ static struct plat_sci_port scif2_platform_data = { ...@@ -245,7 +243,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 82, 82, 82, 82 }, .irqs = { 82, 82, 82, 82 },
.clk = "scif2",
}; };
static struct platform_device scif2_device = { static struct platform_device scif2_device = {
...@@ -261,7 +258,6 @@ static struct plat_sci_port scif3_platform_data = { ...@@ -261,7 +258,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 56, 56, 56, 56 }, .irqs = { 56, 56, 56, 56 },
.clk = "scif3",
}; };
static struct platform_device scif3_device = { static struct platform_device scif3_device = {
...@@ -277,7 +273,6 @@ static struct plat_sci_port scif4_platform_data = { ...@@ -277,7 +273,6 @@ static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 88, 88, 88, 88 }, .irqs = { 88, 88, 88, 88 },
.clk = "scif4",
}; };
static struct platform_device scif4_device = { static struct platform_device scif4_device = {
...@@ -293,7 +288,6 @@ static struct plat_sci_port scif5_platform_data = { ...@@ -293,7 +288,6 @@ static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIFA, .type = PORT_SCIFA,
.irqs = { 109, 109, 109, 109 }, .irqs = { 109, 109, 109, 109 },
.clk = "scif5",
}; };
static struct platform_device scif5_device = { static struct platform_device scif5_device = {
......
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
浏览文件 @ c7ed1ab3
...@@ -25,7 +25,6 @@ static struct plat_sci_port scif0_platform_data = { ...@@ -25,7 +25,6 @@ static struct plat_sci_port scif0_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 40, 40, 40, 40 }, .irqs = { 40, 40, 40, 40 },
.clk = "scif_fck",
}; };
static struct platform_device scif0_device = { static struct platform_device scif0_device = {
...@@ -41,7 +40,6 @@ static struct plat_sci_port scif1_platform_data = { ...@@ -41,7 +40,6 @@ static struct plat_sci_port scif1_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 44, 44, 44, 44 }, .irqs = { 44, 44, 44, 44 },
.clk = "scif_fck",
}; };
static struct platform_device scif1_device = { static struct platform_device scif1_device = {
...@@ -57,7 +55,6 @@ static struct plat_sci_port scif2_platform_data = { ...@@ -57,7 +55,6 @@ static struct plat_sci_port scif2_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 60, 60, 60, 60 }, .irqs = { 60, 60, 60, 60 },
.clk = "scif_fck",
}; };
static struct platform_device scif2_device = { static struct platform_device scif2_device = {
...@@ -73,7 +70,6 @@ static struct plat_sci_port scif3_platform_data = { ...@@ -73,7 +70,6 @@ static struct plat_sci_port scif3_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 61, 61, 61, 61 }, .irqs = { 61, 61, 61, 61 },
.clk = "scif_fck",
}; };
static struct platform_device scif3_device = { static struct platform_device scif3_device = {
...@@ -89,7 +85,6 @@ static struct plat_sci_port scif4_platform_data = { ...@@ -89,7 +85,6 @@ static struct plat_sci_port scif4_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 62, 62, 62, 62 }, .irqs = { 62, 62, 62, 62 },
.clk = "scif_fck",
}; };
static struct platform_device scif4_device = { static struct platform_device scif4_device = {
...@@ -105,7 +100,6 @@ static struct plat_sci_port scif5_platform_data = { ...@@ -105,7 +100,6 @@ static struct plat_sci_port scif5_platform_data = {
.flags = UPF_BOOT_AUTOCONF, .flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF, .type = PORT_SCIF,
.irqs = { 63, 63, 63, 63 }, .irqs = { 63, 63, 63, 63 },
.clk = "scif_fck",
}; };
static struct platform_device scif5_device = { static struct platform_device scif5_device = {
......
drivers/serial/sh-sci.c
浏览文件 @ c7ed1ab3
...@@ -83,8 +83,8 @@ struct sci_port { ...@@ -83,8 +83,8 @@ struct sci_port {
/* Interface clock */ /* Interface clock */
struct clk *iclk; struct clk *iclk;
/* Data clock */ /* Function clock */
struct clk *dclk; struct clk *fclk;
struct list_head node; struct list_head node;
struct dma_chan *chan_tx; struct dma_chan *chan_tx;
...@@ -803,7 +803,7 @@ static int sci_notifier(struct notifier_block *self, ...@@ -803,7 +803,7 @@ static int sci_notifier(struct notifier_block *self,
(phase == CPUFREQ_RESUMECHANGE)) { (phase == CPUFREQ_RESUMECHANGE)) {
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
list_for_each_entry(sci_port, &priv->ports, node) list_for_each_entry(sci_port, &priv->ports, node)
sci_port->port.uartclk = clk_get_rate(sci_port->dclk); sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
} }
...@@ -814,21 +814,17 @@ static void sci_clk_enable(struct uart_port *port) ...@@ -814,21 +814,17 @@ static void sci_clk_enable(struct uart_port *port)
{ {
struct sci_port *sci_port = to_sci_port(port); struct sci_port *sci_port = to_sci_port(port);
clk_enable(sci_port->dclk); clk_enable(sci_port->iclk);
sci_port->port.uartclk = clk_get_rate(sci_port->dclk); sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
clk_enable(sci_port->fclk);
if (sci_port->iclk)
clk_enable(sci_port->iclk);
} }
static void sci_clk_disable(struct uart_port *port) static void sci_clk_disable(struct uart_port *port)
{ {
struct sci_port *sci_port = to_sci_port(port); struct sci_port *sci_port = to_sci_port(port);
if (sci_port->iclk) clk_disable(sci_port->fclk);
clk_disable(sci_port->iclk); clk_disable(sci_port->iclk);
clk_disable(sci_port->dclk);
} }
static int sci_request_irq(struct sci_port *port) static int sci_request_irq(struct sci_port *port)
...@@ -1557,10 +1553,10 @@ static struct uart_ops sci_uart_ops = { ...@@ -1557,10 +1553,10 @@ static struct uart_ops sci_uart_ops = {
#endif #endif
}; };
static void __devinit sci_init_single(struct platform_device *dev, static int __devinit sci_init_single(struct platform_device *dev,
struct sci_port *sci_port, struct sci_port *sci_port,
unsigned int index, unsigned int index,
struct plat_sci_port *p) struct plat_sci_port *p)
{ {
struct uart_port *port = &sci_port->port; struct uart_port *port = &sci_port->port;
...@@ -1581,8 +1577,23 @@ static void __devinit sci_init_single(struct platform_device *dev, ...@@ -1581,8 +1577,23 @@ static void __devinit sci_init_single(struct platform_device *dev,
} }
if (dev) { if (dev) {
sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL; sci_port->iclk = clk_get(&dev->dev, "sci_ick");
sci_port->dclk = clk_get(&dev->dev, "peripheral_clk"); if (IS_ERR(sci_port->iclk)) {
sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
if (IS_ERR(sci_port->iclk)) {
dev_err(&dev->dev, "can't get iclk\n");
return PTR_ERR(sci_port->iclk);
}
}
/*
* The function clock is optional, ignore it if we can't
* find it.
*/
sci_port->fclk = clk_get(&dev->dev, "sci_fck");
if (IS_ERR(sci_port->fclk))
sci_port->fclk = NULL;
sci_port->enable = sci_clk_enable; sci_port->enable = sci_clk_enable;
sci_port->disable = sci_clk_disable; sci_port->disable = sci_clk_disable;
port->dev = &dev->dev; port->dev = &dev->dev;
...@@ -1609,6 +1620,7 @@ static void __devinit sci_init_single(struct platform_device *dev, ...@@ -1609,6 +1620,7 @@ static void __devinit sci_init_single(struct platform_device *dev,
#endif #endif
memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs)); memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
return 0;
} }
#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
...@@ -1758,8 +1770,11 @@ static int sci_remove(struct platform_device *dev) ...@@ -1758,8 +1770,11 @@ static int sci_remove(struct platform_device *dev)
cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
list_for_each_entry(p, &priv->ports, node) list_for_each_entry(p, &priv->ports, node) {
uart_remove_one_port(&sci_uart_driver, &p->port); uart_remove_one_port(&sci_uart_driver, &p->port);
clk_put(p->iclk);
clk_put(p->fclk);
}
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
kfree(priv); kfree(priv);
...@@ -1785,7 +1800,9 @@ static int __devinit sci_probe_single(struct platform_device *dev, ...@@ -1785,7 +1800,9 @@ static int __devinit sci_probe_single(struct platform_device *dev,
return 0; return 0;
} }
sci_init_single(dev, sciport, index, p); ret = sci_init_single(dev, sciport, index, p);
if (ret)
return ret;
ret = uart_add_one_port(&sci_uart_driver, &sciport->port); ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
if (ret) if (ret)
......
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