提交 c79ee7d8 编写于 作者: M Monk Liu 提交者: Alex Deucher

drm/amdgpu:cleanup GMC & gart garbage function

for gart_ram_alloc/free, they are never used in driver thus
ripe them out totally.

for gart_vram_pin/unpin, they are not needed becuase we can
use bo_creat_kernel/free to replace the original manual way
in the gart_vram_alloc/free, thus gart_vram_pin/unpin can
also be riped out.
Signed-off-by: NMonk Liu <Monk.Liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 11c6b82a
...@@ -56,63 +56,6 @@ ...@@ -56,63 +56,6 @@
* Common GART table functions. * Common GART table functions.
*/ */
/**
* amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
*
* @adev: amdgpu_device pointer
*
* Allocate system memory for GART page table
* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
* gart table to be in system memory.
* Returns 0 for success, -ENOMEM for failure.
*/
int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
{
void *ptr;
ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
&adev->gart.table_addr);
if (ptr == NULL) {
return -ENOMEM;
}
#ifdef CONFIG_X86
if (0) {
set_memory_uc((unsigned long)ptr,
adev->gart.table_size >> PAGE_SHIFT);
}
#endif
adev->gart.ptr = ptr;
memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
return 0;
}
/**
* amdgpu_gart_table_ram_free - free system ram for gart page table
*
* @adev: amdgpu_device pointer
*
* Free system memory for GART page table
* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
* gart table to be in system memory.
*/
void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
{
if (adev->gart.ptr == NULL) {
return;
}
#ifdef CONFIG_X86
if (0) {
set_memory_wb((unsigned long)adev->gart.ptr,
adev->gart.table_size >> PAGE_SHIFT);
}
#endif
pci_free_consistent(adev->pdev, adev->gart.table_size,
(void *)adev->gart.ptr,
adev->gart.table_addr);
adev->gart.ptr = NULL;
adev->gart.table_addr = 0;
}
/** /**
* amdgpu_gart_table_vram_alloc - allocate vram for gart page table * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
* *
...@@ -125,75 +68,9 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) ...@@ -125,75 +68,9 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
*/ */
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
{ {
int r; return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.robj,
if (adev->gart.robj == NULL) { &adev->gart.table_addr, &adev->gart.ptr);
r = amdgpu_bo_create(adev, adev->gart.table_size,
PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
NULL, NULL, 0, &adev->gart.robj);
if (r) {
return r;
}
}
return 0;
}
/**
* amdgpu_gart_table_vram_pin - pin gart page table in vram
*
* @adev: amdgpu_device pointer
*
* Pin the GART page table in vram so it will not be moved
* by the memory manager (pcie r4xx, r5xx+). These asics require the
* gart table to be in video memory.
* Returns 0 for success, error for failure.
*/
int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
{
uint64_t gpu_addr;
int r;
r = amdgpu_bo_reserve(adev->gart.robj, false);
if (unlikely(r != 0))
return r;
r = amdgpu_bo_pin(adev->gart.robj,
AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
if (r) {
amdgpu_bo_unreserve(adev->gart.robj);
return r;
}
r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
if (r)
amdgpu_bo_unpin(adev->gart.robj);
amdgpu_bo_unreserve(adev->gart.robj);
adev->gart.table_addr = gpu_addr;
return r;
}
/**
* amdgpu_gart_table_vram_unpin - unpin gart page table in vram
*
* @adev: amdgpu_device pointer
*
* Unpin the GART page table in vram (pcie r4xx, r5xx+).
* These asics require the gart table to be in video memory.
*/
void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
{
int r;
if (adev->gart.robj == NULL) {
return;
}
r = amdgpu_bo_reserve(adev->gart.robj, true);
if (likely(r == 0)) {
amdgpu_bo_kunmap(adev->gart.robj);
amdgpu_bo_unpin(adev->gart.robj);
amdgpu_bo_unreserve(adev->gart.robj);
adev->gart.ptr = NULL;
}
} }
/** /**
...@@ -207,10 +84,9 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) ...@@ -207,10 +84,9 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
*/ */
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
{ {
if (adev->gart.robj == NULL) { amdgpu_bo_free_kernel(&adev->gart.robj,
return; &adev->gart.table_addr,
} &adev->gart.ptr);
amdgpu_bo_unref(&adev->gart.robj);
} }
/* /*
......
...@@ -56,12 +56,8 @@ struct amdgpu_gart { ...@@ -56,12 +56,8 @@ struct amdgpu_gart {
const struct amdgpu_gart_funcs *gart_funcs; const struct amdgpu_gart_funcs *gart_funcs;
}; };
int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
int amdgpu_gart_init(struct amdgpu_device *adev); int amdgpu_gart_init(struct amdgpu_device *adev);
void amdgpu_gart_fini(struct amdgpu_device *adev); void amdgpu_gart_fini(struct amdgpu_device *adev);
int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
......
...@@ -1397,8 +1397,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) ...@@ -1397,8 +1397,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
void amdgpu_ttm_fini(struct amdgpu_device *adev) void amdgpu_ttm_fini(struct amdgpu_device *adev)
{ {
int r;
if (!adev->mman.initialized) if (!adev->mman.initialized)
return; return;
......
...@@ -483,16 +483,14 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) ...@@ -483,16 +483,14 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
{ {
int r, i; int i;
u32 field; u32 field;
if (adev->gart.robj == NULL) { if (adev->gart.robj == NULL) {
dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
return -EINVAL; return -EINVAL;
} }
r = amdgpu_gart_table_vram_pin(adev);
if (r)
return r;
/* Setup TLB control */ /* Setup TLB control */
WREG32(mmMC_VM_MX_L1_TLB_CNTL, WREG32(mmMC_VM_MX_L1_TLB_CNTL,
(0xA << 7) | (0xA << 7) |
...@@ -619,7 +617,6 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) ...@@ -619,7 +617,6 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
WREG32(mmVM_L2_CNTL3, WREG32(mmVM_L2_CNTL3,
VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
(0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
amdgpu_gart_table_vram_unpin(adev);
} }
static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
......
...@@ -588,16 +588,14 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) ...@@ -588,16 +588,14 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
*/ */
static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
{ {
int r, i; int i;
u32 tmp, field; u32 tmp, field;
if (adev->gart.robj == NULL) { if (adev->gart.robj == NULL) {
dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
return -EINVAL; return -EINVAL;
} }
r = amdgpu_gart_table_vram_pin(adev);
if (r)
return r;
/* Setup TLB control */ /* Setup TLB control */
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
...@@ -730,7 +728,6 @@ static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) ...@@ -730,7 +728,6 @@ static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
WREG32(mmVM_L2_CNTL, tmp); WREG32(mmVM_L2_CNTL, tmp);
WREG32(mmVM_L2_CNTL2, 0); WREG32(mmVM_L2_CNTL2, 0);
amdgpu_gart_table_vram_unpin(adev);
} }
/** /**
......
...@@ -787,16 +787,14 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) ...@@ -787,16 +787,14 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
*/ */
static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
{ {
int r, i; int i;
u32 tmp, field; u32 tmp, field;
if (adev->gart.robj == NULL) { if (adev->gart.robj == NULL) {
dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
return -EINVAL; return -EINVAL;
} }
r = amdgpu_gart_table_vram_pin(adev);
if (r)
return r;
/* Setup TLB control */ /* Setup TLB control */
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
...@@ -946,7 +944,6 @@ static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) ...@@ -946,7 +944,6 @@ static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
WREG32(mmVM_L2_CNTL, tmp); WREG32(mmVM_L2_CNTL, tmp);
WREG32(mmVM_L2_CNTL2, 0); WREG32(mmVM_L2_CNTL2, 0);
amdgpu_gart_table_vram_unpin(adev);
} }
/** /**
......
...@@ -869,7 +869,7 @@ static int gmc_v9_0_sw_init(void *handle) ...@@ -869,7 +869,7 @@ static int gmc_v9_0_sw_init(void *handle)
} }
/** /**
* gmc_v8_0_gart_fini - vm fini callback * gmc_v9_0_gart_fini - vm fini callback
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* *
...@@ -933,9 +933,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) ...@@ -933,9 +933,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
return -EINVAL; return -EINVAL;
} }
r = amdgpu_gart_table_vram_pin(adev);
if (r)
return r;
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
...@@ -1013,7 +1010,6 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) ...@@ -1013,7 +1010,6 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
{ {
gfxhub_v1_0_gart_disable(adev); gfxhub_v1_0_gart_disable(adev);
mmhub_v1_0_gart_disable(adev); mmhub_v1_0_gart_disable(adev);
amdgpu_gart_table_vram_unpin(adev);
} }
static int gmc_v9_0_hw_fini(void *handle) static int gmc_v9_0_hw_fini(void *handle)
......
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