提交 b1394dc1 编写于 作者: S Smitha T Murthy 提交者: Mauro Carvalho Chehab

media: s5p-mfc: Adding initial support for MFC v10.10

Adding the support for MFC v10.10, with new register file and
necessary hw control, decoder, encoder and structural changes.
Signed-off-by: NSmitha T Murthy <smitha.t@samsung.com>
Reviewed-by: NAndrzej Hajda <a.hajda@samsung.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>
上级 f1a355bf
......@@ -13,6 +13,7 @@ Required properties:
(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
(e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
(f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
- reg : Physical base address of the IP registers and length of memory
mapped region.
......
/* SPDX-License-Identifier: GPL-2.0 */
/*
*
* Copyright (c) 2017 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Register definition file for Samsung MFC V10.x Interface (FIMV) driver
*
*/
#ifndef _REGS_MFC_V10_H
#define _REGS_MFC_V10_H
#include <linux/sizes.h>
#include "regs-mfc-v8.h"
/* MFCv10 register definitions*/
#define S5P_FIMV_MFC_CLOCK_OFF_V10 0x7120
#define S5P_FIMV_MFC_STATE_V10 0x7124
/* MFCv10 Context buffer sizes */
#define MFC_CTX_BUF_SIZE_V10 (30 * SZ_1K)
#define MFC_H264_DEC_CTX_BUF_SIZE_V10 (2 * SZ_1M)
#define MFC_OTHER_DEC_CTX_BUF_SIZE_V10 (20 * SZ_1K)
#define MFC_H264_ENC_CTX_BUF_SIZE_V10 (100 * SZ_1K)
#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10 (15 * SZ_1K)
/* MFCv10 variant defines */
#define MAX_FW_SIZE_V10 (SZ_1M)
#define MAX_CPB_SIZE_V10 (3 * SZ_1M)
#define MFC_VERSION_V10 0xA0
#define MFC_NUM_PORTS_V10 1
#endif /*_REGS_MFC_V10_H*/
......@@ -1607,6 +1607,28 @@ static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
.num_clocks = 3,
};
static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
.dev_ctx = MFC_CTX_BUF_SIZE_V10,
.h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V10,
.other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
.h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V10,
.other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
};
static struct s5p_mfc_buf_size buf_size_v10 = {
.fw = MAX_FW_SIZE_V10,
.cpb = MAX_CPB_SIZE_V10,
.priv = &mfc_buf_size_v10,
};
static struct s5p_mfc_variant mfc_drvdata_v10 = {
.version = MFC_VERSION_V10,
.version_bit = MFC_V10_BIT,
.port_num = MFC_NUM_PORTS_V10,
.buf_size = &buf_size_v10,
.fw_name[0] = "s5p-mfc-v10.fw",
};
static const struct of_device_id exynos_mfc_match[] = {
{
.compatible = "samsung,mfc-v5",
......@@ -1623,6 +1645,9 @@ static const struct of_device_id exynos_mfc_match[] = {
}, {
.compatible = "samsung,exynos5433-mfc",
.data = &mfc_drvdata_v8_5433,
}, {
.compatible = "samsung,mfc-v10",
.data = &mfc_drvdata_v10,
},
{},
};
......
......@@ -23,7 +23,7 @@
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-v4l2.h>
#include "regs-mfc.h"
#include "regs-mfc-v8.h"
#include "regs-mfc-v10.h"
#define S5P_MFC_NAME "s5p-mfc"
......@@ -715,11 +715,18 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0)
#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0)
#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0)
#define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0)
#define MFC_V5_BIT BIT(0)
#define MFC_V6_BIT BIT(1)
#define MFC_V7_BIT BIT(2)
#define MFC_V8_BIT BIT(3)
#define MFC_V10_BIT BIT(5)
#define MFC_V5PLUS_BITS (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
MFC_V8_BIT | MFC_V10_BIT)
#define MFC_V6PLUS_BITS (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
MFC_V10_BIT)
#define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT)
#endif /* S5P_MFC_COMMON_H_ */
......@@ -239,6 +239,10 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
}
else
mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
if (IS_MFCV10(dev))
mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
mfc_debug(2, "Will now wait for completion of firmware transfer\n");
if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
mfc_err("Failed to load firmware\n");
......
......@@ -54,7 +54,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_NONE,
.type = MFC_FMT_RAW,
.num_planes = 2,
.versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
.versions = MFC_V6PLUS_BITS,
},
{
.name = "4:2:0 2 Planes Y/CrCb",
......@@ -62,7 +62,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_NONE,
.type = MFC_FMT_RAW,
.num_planes = 2,
.versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
.versions = MFC_V6PLUS_BITS,
},
{
.name = "H264 Encoded Stream",
......@@ -70,8 +70,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_H264_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "H264/MVC Encoded Stream",
......@@ -79,7 +78,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_H264_MVC_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
.versions = MFC_V6PLUS_BITS,
},
{
.name = "H263 Encoded Stream",
......@@ -87,8 +86,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_H263_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "MPEG1 Encoded Stream",
......@@ -96,8 +94,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_MPEG2_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "MPEG2 Encoded Stream",
......@@ -105,8 +102,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_MPEG2_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "MPEG4 Encoded Stream",
......@@ -114,8 +110,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_MPEG4_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "XviD Encoded Stream",
......@@ -123,8 +118,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_MPEG4_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "VC1 Encoded Stream",
......@@ -132,8 +126,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_VC1_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "VC1 RCV Encoded Stream",
......@@ -141,8 +134,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_VC1RCV_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "VP8 Encoded Stream",
......@@ -150,7 +142,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_VP8_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
.versions = MFC_V6PLUS_BITS,
},
};
......
......@@ -57,8 +57,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_NONE,
.type = MFC_FMT_RAW,
.num_planes = 2,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "4:2:0 2 Planes Y/CrCb",
......@@ -66,7 +65,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_NONE,
.type = MFC_FMT_RAW,
.num_planes = 2,
.versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
.versions = MFC_V6PLUS_BITS,
},
{
.name = "H264 Encoded Stream",
......@@ -74,8 +73,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_H264_ENC,
.type = MFC_FMT_ENC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "MPEG4 Encoded Stream",
......@@ -83,8 +81,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_MPEG4_ENC,
.type = MFC_FMT_ENC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "H263 Encoded Stream",
......@@ -92,8 +89,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_H263_ENC,
.type = MFC_FMT_ENC,
.num_planes = 1,
.versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
MFC_V8_BIT,
.versions = MFC_V5PLUS_BITS,
},
{
.name = "VP8 Encoded Stream",
......@@ -101,7 +97,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_MFC_CODEC_VP8_ENC,
.type = MFC_FMT_ENC,
.num_planes = 1,
.versions = MFC_V7_BIT | MFC_V8_BIT,
.versions = MFC_V7PLUS_BITS,
},
};
......
......@@ -356,6 +356,7 @@ static int calc_plane(int width, int height)
static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
{
struct s5p_mfc_dev *dev = ctx->dev;
ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
......@@ -372,8 +373,12 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
ctx->img_height);
if (IS_MFCV10(dev))
ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
ctx->img_height);
else
ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
ctx->img_height);
ctx->mv_size = ALIGN(ctx->mv_size, 16);
} else {
ctx->mv_size = 0;
......
......@@ -24,6 +24,8 @@
#define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, 16)
#define S5P_MFC_DEC_MV_SIZE_V6(x, y) (MB_WIDTH(x) * \
(((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)
#define S5P_MFC_DEC_MV_SIZE_V10(x, y) (MB_WIDTH(x) * \
(((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)
/* Definition */
#define ENC_MULTI_SLICE_MB_MAX ((1 << 30) - 1)
......
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