提交 b1277a22 编写于 作者: C Christian König 提交者: Bjorn Helgaas

PCI: Cleanup PCI_REBAR_CTRL_BAR_SHIFT handling

Cleanup PCI_REBAR_CTRL_BAR_SHIFT handling.  That was hard coded instead of
properly defined in the header for some reason.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
上级 d3252ace
...@@ -1193,7 +1193,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev) ...@@ -1193,7 +1193,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev)
res = pdev->resource + bar_idx; res = pdev->resource + bar_idx;
size = order_base_2((resource_size(res) >> 20) | 1) - 1; size = order_base_2((resource_size(res) >> 20) | 1) - 1;
ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
ctrl |= size << 8; ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
} }
} }
...@@ -3098,7 +3098,7 @@ int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) ...@@ -3098,7 +3098,7 @@ int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
return pos; return pos;
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8; return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
} }
/** /**
...@@ -3121,7 +3121,7 @@ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) ...@@ -3121,7 +3121,7 @@ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
ctrl |= size << 8; ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
return 0; return 0;
} }
......
...@@ -960,8 +960,9 @@ ...@@ -960,8 +960,9 @@
#define PCI_REBAR_CTRL 8 /* control register */ #define PCI_REBAR_CTRL 8 /* control register */
#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ #define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */
#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ #define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */ #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */
#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */ #define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */
#define PCI_REBAR_CTRL_BAR_SHIFT 8 /* shift for BAR size */
/* Dynamic Power Allocation */ /* Dynamic Power Allocation */
#define PCI_DPA_CAP 4 /* capability register */ #define PCI_DPA_CAP 4 /* capability register */
......
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