V4L/DVB (12222): gspca - stv06xx-hdcs: Fix sensor sequence bug
All hdcs registers use bit 0 as a read/write flag and needs to be shifted one bit to the left. This wasn't accounted for when doing a sequence of writes. Signed-off-by: NErik Andrén <erik.andren@gmail.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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