Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openanolis
cloud-kernel
提交
ab285892
cloud-kernel
项目概览
openanolis
/
cloud-kernel
大约 1 年 前同步成功
通知
158
Star
36
Fork
7
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
10
列表
看板
标记
里程碑
合并请求
2
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
cloud-kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
10
Issue
10
列表
看板
标记
里程碑
合并请求
2
合并请求
2
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
ab285892
编写于
8月 14, 2012
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nv84/fifo: add support for dma channel class
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
a7c6e75e
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
81 addition
and
7 deletion
+81
-7
drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
+1
-0
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+79
-7
drivers/gpu/drm/nouveau/core/include/core/class.h
drivers/gpu/drm/nouveau/core/include/core/class.h
+1
-0
未找到文件。
drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
浏览文件 @
ab285892
...
...
@@ -110,6 +110,7 @@ nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
switch
(
nv_mclass
(
parent
))
{
case
0x506f
:
case
0x826e
:
case
0x826f
:
ret
=
dmaeng
->
bind
(
dmaeng
,
*
pobject
,
&
dmaobj
->
base
,
&
gpuobj
);
nouveau_object_ref
(
NULL
,
pobject
);
...
...
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
浏览文件 @
ab285892
...
...
@@ -147,10 +147,71 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
}
static
int
nv84_fifo_chan_ctor
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nouveau_object
**
pobject
)
nv84_fifo_chan_ctor_dma
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nouveau_object
**
pobject
)
{
struct
nouveau_bar
*
bar
=
nouveau_bar
(
parent
);
struct
nv50_fifo_base
*
base
=
(
void
*
)
parent
;
struct
nv50_fifo_chan
*
chan
;
struct
nv03_channel_dma_class
*
args
=
data
;
int
ret
;
if
(
size
<
sizeof
(
*
args
))
return
-
EINVAL
;
ret
=
nouveau_fifo_channel_create
(
parent
,
engine
,
oclass
,
0
,
0xc00000
,
0x2000
,
args
->
pushbuf
,
(
1
<<
NVDEV_ENGINE_DMAOBJ
)
|
(
1
<<
NVDEV_ENGINE_SW
)
|
(
1
<<
NVDEV_ENGINE_GR
)
|
(
1
<<
NVDEV_ENGINE_MPEG
)
|
(
1
<<
NVDEV_ENGINE_ME
)
|
(
1
<<
NVDEV_ENGINE_VP
)
|
(
1
<<
NVDEV_ENGINE_CRYPT
)
|
(
1
<<
NVDEV_ENGINE_BSP
)
|
(
1
<<
NVDEV_ENGINE_PPP
)
|
(
1
<<
NVDEV_ENGINE_COPY0
)
|
(
1
<<
NVDEV_ENGINE_UNK1C1
),
&
chan
);
*
pobject
=
nv_object
(
chan
);
if
(
ret
)
return
ret
;
ret
=
nouveau_ramht_new
(
parent
,
parent
,
0x8000
,
16
,
&
chan
->
ramht
);
if
(
ret
)
return
ret
;
nv_parent
(
chan
)
->
context_attach
=
nv84_fifo_context_attach
;
nv_parent
(
chan
)
->
context_detach
=
nv84_fifo_context_detach
;
nv_parent
(
chan
)
->
object_attach
=
nv84_fifo_object_attach
;
nv_parent
(
chan
)
->
object_detach
=
nv50_fifo_object_detach
;
nv_wo32
(
base
->
ramfc
,
0x08
,
lower_32_bits
(
args
->
offset
));
nv_wo32
(
base
->
ramfc
,
0x0c
,
upper_32_bits
(
args
->
offset
));
nv_wo32
(
base
->
ramfc
,
0x10
,
lower_32_bits
(
args
->
offset
));
nv_wo32
(
base
->
ramfc
,
0x14
,
upper_32_bits
(
args
->
offset
));
nv_wo32
(
base
->
ramfc
,
0x3c
,
0x003f6078
);
nv_wo32
(
base
->
ramfc
,
0x44
,
0x01003fff
);
nv_wo32
(
base
->
ramfc
,
0x48
,
chan
->
base
.
pushgpu
->
node
->
offset
>>
4
);
nv_wo32
(
base
->
ramfc
,
0x4c
,
0xffffffff
);
nv_wo32
(
base
->
ramfc
,
0x60
,
0x7fffffff
);
nv_wo32
(
base
->
ramfc
,
0x78
,
0x00000000
);
nv_wo32
(
base
->
ramfc
,
0x7c
,
0x30000001
);
nv_wo32
(
base
->
ramfc
,
0x80
,
((
chan
->
ramht
->
bits
-
9
)
<<
27
)
|
(
4
<<
24
)
/* SEARCH_FULL */
|
(
chan
->
ramht
->
base
.
node
->
offset
>>
4
));
nv_wo32
(
base
->
ramfc
,
0x88
,
base
->
cache
->
addr
>>
10
);
nv_wo32
(
base
->
ramfc
,
0x98
,
nv_gpuobj
(
base
)
->
addr
>>
12
);
bar
->
flush
(
bar
);
return
0
;
}
static
int
nv84_fifo_chan_ctor_ind
(
struct
nouveau_object
*
parent
,
struct
nouveau_object
*
engine
,
struct
nouveau_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nouveau_object
**
pobject
)
{
struct
nouveau_bar
*
bar
=
nouveau_bar
(
parent
);
struct
nv50_fifo_base
*
base
=
(
void
*
)
parent
;
...
...
@@ -228,8 +289,18 @@ nv84_fifo_chan_init(struct nouveau_object *object)
}
static
struct
nouveau_ofuncs
nv84_fifo_ofuncs
=
{
.
ctor
=
nv84_fifo_chan_ctor
,
nv84_fifo_ofuncs_dma
=
{
.
ctor
=
nv84_fifo_chan_ctor_dma
,
.
dtor
=
nv50_fifo_chan_dtor
,
.
init
=
nv84_fifo_chan_init
,
.
fini
=
nv50_fifo_chan_fini
,
.
rd32
=
_nouveau_fifo_channel_rd32
,
.
wr32
=
_nouveau_fifo_channel_wr32
,
};
static
struct
nouveau_ofuncs
nv84_fifo_ofuncs_ind
=
{
.
ctor
=
nv84_fifo_chan_ctor_ind
,
.
dtor
=
nv50_fifo_chan_dtor
,
.
init
=
nv84_fifo_chan_init
,
.
fini
=
nv50_fifo_chan_fini
,
...
...
@@ -239,7 +310,8 @@ nv84_fifo_ofuncs = {
static
struct
nouveau_oclass
nv84_fifo_sclass
[]
=
{
{
0x826f
,
&
nv84_fifo_ofuncs
},
{
0x826e
,
&
nv84_fifo_ofuncs_dma
},
{
0x826f
,
&
nv84_fifo_ofuncs_ind
},
{}
};
...
...
drivers/gpu/drm/nouveau/core/include/core/class.h
浏览文件 @
ab285892
...
...
@@ -55,6 +55,7 @@ struct nv_dma_class {
* 006e: NV10_CHANNEL_DMA
* 176e: NV17_CHANNEL_DMA
* 406e: NV40_CHANNEL_DMA
* 826e: NV84_CHANNEL_DMA
*/
struct
nv03_channel_dma_class
{
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录