提交 a9d43091 编写于 作者: L Lothar Wassmann 提交者: Greg Kroah-Hartman

USB: NXP ISP1362 USB host driver

Signed-off-by: NLothar Wassmann <LW@KARO-electronics.de>
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 e9238221
......@@ -16,6 +16,7 @@ obj-$(CONFIG_USB_UHCI_HCD) += host/
obj-$(CONFIG_USB_FHCI_HCD) += host/
obj-$(CONFIG_USB_XHCI_HCD) += host/
obj-$(CONFIG_USB_SL811_HCD) += host/
obj-$(CONFIG_USB_ISP1362_HCD) += host/
obj-$(CONFIG_USB_U132_HCD) += host/
obj-$(CONFIG_USB_R8A66597_HCD) += host/
obj-$(CONFIG_USB_HWA_HCD) += host/
......
......@@ -159,6 +159,18 @@ config USB_ISP1760_HCD
To compile this driver as a module, choose M here: the
module will be called isp1760.
config USB_ISP1362_HCD
tristate "ISP1362 HCD support"
depends on USB
default N
---help---
Supports the Philips ISP1362 chip as a host controller
This driver does not support isochronous transfers.
To compile this driver as a module, choose M here: the
module will be called isp1362-hcd.
config USB_OHCI_HCD
tristate "OHCI HCD support"
depends on USB && USB_ARCH_HAS_OHCI
......
......@@ -21,6 +21,7 @@ obj-$(CONFIG_PCI) += pci-quirks.o
obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o
obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
obj-$(CONFIG_USB_ISP1362_HCD) += isp1362-hcd.o
obj-$(CONFIG_USB_OHCI_HCD) += ohci-hcd.o
obj-$(CONFIG_USB_UHCI_HCD) += uhci-hcd.o
obj-$(CONFIG_USB_FHCI_HCD) += fhci.o
......
此差异已折叠。
此差异已折叠。
/*
* board initialization code should put one of these into dev->platform_data
* and place the isp1362 onto platform_bus.
*/
#ifndef __LINUX_USB_ISP1362_H__
#define __LINUX_USB_ISP1362_H__
struct isp1362_platform_data {
/* Enable internal pulldown resistors on downstream ports */
unsigned sel15Kres:1;
/* Clock cannot be stopped */
unsigned clknotstop:1;
/* On-chip overcurrent protection */
unsigned oc_enable:1;
/* INT output polarity */
unsigned int_act_high:1;
/* INT edge or level triggered */
unsigned int_edge_triggered:1;
/* DREQ output polarity */
unsigned dreq_act_high:1;
/* DACK input polarity */
unsigned dack_act_high:1;
/* chip can be resumed via H_WAKEUP pin */
unsigned remote_wakeup_connected:1;
/* Switch or not to switch (keep always powered) */
unsigned no_power_switching:1;
/* Ganged port power switching (0) or individual port power switching (1) */
unsigned power_switching_mode:1;
/* Given port_power, msec/2 after power on till power good */
u8 potpg;
/* Hardware reset set/clear */
void (*reset) (struct device *dev, int set);
/* Clock start/stop */
void (*clock) (struct device *dev, int start);
/* Inter-io delay (ns). The chip is picky about access timings; it
* expects at least:
* 110ns delay between consecutive accesses to DATA_REG,
* 300ns delay between access to ADDR_REG and DATA_REG (registers)
* 462ns delay between access to ADDR_REG and DATA_REG (buffer memory)
* WE MUST NOT be activated during these intervals (even without CS!)
*/
void (*delay) (struct device *dev, unsigned int delay);
};
#endif
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