提交 a2b23fe0 编写于 作者: J Jesse Barnes 提交者: Daniel Vetter

drm/i915/vlv: honor i915_enable_rc6 boot param on VLV

Disabling it isn't really an option on these platforms, but having it
available for power comparisons is useful.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
上级 040d2baa
...@@ -3788,7 +3788,7 @@ static void valleyview_enable_rps(struct drm_device *dev) ...@@ -3788,7 +3788,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring; struct intel_ring_buffer *ring;
u32 gtfifodbg, val; u32 gtfifodbg, val, rc6_mode = 0;
int i; int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
...@@ -3828,8 +3828,9 @@ static void valleyview_enable_rps(struct drm_device *dev) ...@@ -3828,8 +3828,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
/* allows RC6 residency counter to work */ /* allows RC6 residency counter to work */
I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3)); I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
I915_WRITE(GEN6_RC_CONTROL, if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
GEN7_RC_CTL_TO_MODE); rc6_mode = GEN7_RC_CTL_TO_MODE;
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
switch ((val >> 6) & 3) { switch ((val >> 6) & 3) {
......
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