提交 a26bce12 编写于 作者: W Will Deacon 提交者: Russell King

ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores

ARMv6 cores do not implement the DBGOSLAR register, so we don't need to
try and clear it on boot. Furthermore, the VCR is zeroed out of reset,
so we don't need to zero it explicitly when a CPU comes online.
Tested-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
上级 c825dda9
...@@ -892,6 +892,10 @@ static void reset_ctrl_regs(void *unused) ...@@ -892,6 +892,10 @@ static void reset_ctrl_regs(void *unused)
* later on. * later on.
*/ */
switch (debug_arch) { switch (debug_arch) {
case ARM_DEBUG_ARCH_V6:
case ARM_DEBUG_ARCH_V6_1:
/* ARMv6 cores just need to reset the registers. */
goto reset_regs;
case ARM_DEBUG_ARCH_V7_ECP14: case ARM_DEBUG_ARCH_V7_ECP14:
/* /*
* Ensure sticky power-down is clear (i.e. debug logic is * Ensure sticky power-down is clear (i.e. debug logic is
...@@ -931,6 +935,7 @@ static void reset_ctrl_regs(void *unused) ...@@ -931,6 +935,7 @@ static void reset_ctrl_regs(void *unused)
asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
isb(); isb();
reset_regs:
if (enable_monitor_mode()) if (enable_monitor_mode())
return; return;
......
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